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| 1 datasheet buck-boost narrow vdc battery charger with smbus interface and usb otg ISL9238, ISL9238a the ISL9238 and ISL9238a are buck-boost narrow output voltage dc (nvdc) chargers. the ISL9238 and ISL9238a provide the nvdc charging function, system bus regulation and protection features for tablet, ultrabook, notebook, power bank and any usb-c interface platform. intersil?s advanced r3? technology is used to provide high light-load efficiency and fast transient response. in charging mode th e ISL9238 and ISL9238a takes input power from a wide range of dc power sources (conventional ac/dc charger adapters, usb pd ports, tr avel adapters, etc.) and safely charges battery packs with up to 4-series cell li-ion batteries. as a nvdc topology charger, it al so regulates the system output to a narrow dc range for stable sy stem bus voltage. the system power can be provided from the adapter, battery or a combination of both. the ISL9238 and isl923 8a can operate with only a battery, only an adapter or both connected. for intel imvp8 compliant systems the ISL9238 an d ISL9238a includes psys (system power monitor) functional ity, which provides an analog signal representing total platform power. the psys output will connect to a wide range of intersil imvp8 core regulators to provide an imvp8 compliant power domain function. the ISL9238 and ISL9238a support reverse buck, boost, or buck-boost operation to input port from 2- to 4-cell batteries. the ISL9238 and ISL9238a have serial communication via smbus/i 2 c that allows programming of many critical parameters to deliver a customized solution. the ISL9238a is exactly same as ISL9238, but it has different smbus addresses for customers who use two battery chargers in one system. features ? buck-boost nvdc charger for 1-, 2 -, 3-, or 4-cell li-ion batteries ? input voltage range 3.2v to 23.4v (no dead zone) ? system output voltage 2.4v to 18.304v ? autonomous charging option (automatic end of charging) ? system power monitor psys output, imvp compliant ?up to 1mhz switching frequency ? adapter current and battery current monitor (amon/bmon) ? prochot# open-drain output, imvp compliant ? allows trickle charging of depleted battery ? ideal diode control in turbo mode ? reverse buck, boost and buck-boost operation from battery ? two-level adapter current limit available ? battery ship mode option ? smbus and auto-increment i 2 c compatible ? package 4x4 32 ld tqfn applications ? 1 to 4-cell tablet, ultrabook, notebook, power bank, and any usb-c interface portable device requiring batteries related literature ? for a full list of related documents please visit our web pages - ISL9238 , ISL9238a product pages figure 1. typical application circuit ISL9238 boot1 phase1 ugate1 vddp lgate1 lgate2 ugate2 phase2 boot2 scl sda vbat csop cson dcin vdd comp psys bgate asgate prochot# acin acok gnd csip csin amon/bmon batgone vadp vbat vsys prog vsys otgpg/cmout adp otgen/cmin q1 q2 q4 q3 r s1 r s2 l1 optional november 9, 2016 fn8877.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2016. all rights reserved intersil (and design) and r3 technology are trademarks ow ned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL9238, ISL9238a 2 fn8877.2 november 9, 2016 submit document feedback table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 simplified application circuit . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 smbus timing specification . . . . . . . . . . . . . . . . . . . . . . . . . 14 gate driver timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . .14 typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 general smbus architecture . . . . . . . . . . . . . . . . . . . . . . . . .18 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 start and stop conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 smbus transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 smbus and i 2 c compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . 19 ISL9238 and ISL9238a smbus commands . . . . . . . . . . . . .19 setting charging current limit . . . . . . . . . . . . . . . . . . . . . . . 21 setting adapter current limit . . . . . . . . . . . . . . . . . . . . . . . . 21 setting two-level adapter current limit duration . . . . . . . . 22 setting maximum char ging voltage or system regulating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 setting minimum syst em voltage . . . . . . . . . . . . . . . . . . . . . . 23 setting prochot# threshold for adapter overcurrent condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 setting prochot# threshold fo r battery over discharging current condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 setting prochot# debo unce time and duration time. . . . 24 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 otg voltage register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 otg current register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 input voltage register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 r3? modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ISL9238 and ISL9238a buck-boost charger with usb otg 33 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 programming charger option . . . . . . . . . . . . . . . . . . . . . . . . . 34 autonomous charging mode. . . . . . . . . . . . . . . . . . . . . . . . . . 35 battery ship mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 de operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 battery learn mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 turbo mode support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 two-level adapter current limit. . . . . . . . . . . . . . . . . . . . . . . 36 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 psys monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 trickle charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 system voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 charger timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 usb otg (on the go) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 stand-alone comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 adapter overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . 39 battery overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . 39 system overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . 39 way overcurrent protection (wocp) . . . . . . . . . . . . . . . . . . . 39 over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . 39 switching power mosfet gate capacitance . . . . . . . . . . . . 39 adapter input filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 general application information . . . . . . . . . . . . . . . . . . . . . . 40 select the lc output filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 select the input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 select the switching power mosfet . . . . . . . . . . . . . . . . . . . 41 select the bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . 41 layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 about intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ISL9238, ISL9238a 3 fn8877.2 november 9, 2016 submit document feedback ordering information part number ( notes 4 , 5 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL9238hrtz ( note 1 ) 9238h -10 to +100 32 ld 4x4 tqfn l32.4x4d ISL9238irtz ( note 2 ) 9238i -40 to +100 32 ld 4x4 tqfn l32.4x4d ISL9238ahrtz ( note 3 ) 9238ah -10 to +100 32 ld 4x4 tqfn l32.4x4d ISL9238eval1z evaluation board notes: 1. add ?-t? suffix for 6k unit, ?-tk? suffix for 1k unit, or ?-t7a? suffix for 250 unit tape and reel options. refer to tb347 for details on reel specifications. 2. add ?-t? suffix for 6k unit tape and reel option. refer to tb347 for details on reel specifications. 3. add ?-t? suffix for 6k unit or ?-tk? suffix for 1k unit tape and reel options. refer to tb347 for details on reel specifications. 4. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 5. for moisture sensitivity level (msl), see product information page for ISL9238 , ISL9238a . for more information on msl, see tech brief tb363 . table 1. key differences between family of parts part number i 2 c read address i 2 c write address ISL9238 0b00010011 (0x13h) 0b00010010 (0x12h) ISL9238a 0b00011011 (0x1bh) 0b00011010 (0x1ah) ISL9238, ISL9238a 4 fn8877.2 november 9, 2016 submit document feedback pin configuration ISL9238, ISL9238a (32 ld 4x4 tqfn) top view bgate vbat psys amon/bmon comp prog otgpg/cmout batgone lgate1 phase1 ugate1 boot1 asgate csin csip adp cson csop vsys boot2 ugate2 phase2 lgate2 vddp acok prochot# scl sda otgen/cmin acin vdd dcin 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 gnd (bottom pad) pin descriptions pin number pin name description bottom pad gnd signal common of the ic. unless otherwise stated, si gnals are referenced to the gnd pin. it should also be used as the thermal pad for heat dissipation. 1 cson battery current sense ??? input. connect to battery curr ent resistor negative input. place a 0.1f ceramic capacitor between csop to cson to provide differential mode filtering. 2 csop battery current sense ?+? input. connect to battery curr ent resistor positive input. place a 0.1f ceramic capacitor between csop to cson to provide differential mode filtering. 3 vsys provides feedback voltage for maxsystemvoltage regulation. 4 boot2 high-side mosfet q4 gate driver supply. connect an mlcc capacitor across the boot2 and phase2 pins. the boot capacitor is charged through an internal boot diode conn ected from the vddp to boot2 pins when the phase2 pin drops below vddp minus the voltage dr op across the internal boot diode. 5 ugate2 high-side mosfet q4 gate drive. 6 phase2 current return path for the high-side mosfet q4 gate dr ive. connect this pin to the no de consisting of the high-side mosfet q4 source, the low-side mosfet q3 drain and the one terminal of the inductor. 7 lgate2 low-side mosfet q3 gate drive. 8 vddp power supply for the gate drivers. connect to vdd pin through a 4.7 resistor and connect a 1f ceramic capacitor to gnd. 9 lgate1 low-side mosfet q2 gate drive. 10 phase1 current return path for the high-side mosfet q1 gate dr ive. connect this pin to the no de consisting of the high-side mosfet q1 source, the low-side mosfet q2 drain and the input terminal of the inductor. 11 ugate1 high-side mosfet q1 gate drive. 12 boot1 high-side mosfet q1 gate driver supply. connect an mlcc capacitor across the boot1 and phase1 pins. the boot capacitor is charged through an internal boot diode conn ected from the vddp to boot1 pins when the phase1 pin drops below vddp minus the voltage dr op across the internal boot diode. ISL9238, ISL9238a 5 fn8877.2 november 9, 2016 submit document feedback 13 asgate gate drive output to the p-channel adapter fet. the use of asgate fets is optional, if it is not used, leave asgate pin floating. when asgate turns on, it is clamped 10v below adp pin voltage. 14 csin adapter current sense ?-? input. 15 csip adapter current sense ?+? input. the modulator also uses this for sensing input voltage in forward mode and output voltage in reverse mode. 16 adp adapter input. used to sense adapter voltage. when adapter voltage is higher than 3.2v, agate is turned on. adp pin is also one of the two internal low power ldo inputs. 17 dcin input of an internal ldo providing power to the ic. connect a diode or from adapter and system outputs. bypass this pin with an mlcc capacitor. 18 vdd output of the internal ldo; provide the bias power for th e internal analog and digital circuit. connect a 1f ceramic capacitor to gnd. if vdd is pulled below 2v more than 1ms, ISL9238 and isl 9238a will reset all the smbus register values to the default. 19 acin adapter voltage sense. use a resistor divider externally to detect adapter voltage. the adapter voltage is valid if the a cin pin voltage is greater than 0.8v. 20 otgen/ cmin otg function enable pin or stand-alone comparator input pin. pull high to enable otg function. the otg function is enable d when the control register is written to select otg mode and when the battery voltage is above 5.2v. when otg function is not selected, this pin is the general purpose stand-alone comparator input. 21 sda smbus data i/o. connect to the data line from the host controller or smart battery. connect a 10k pull-up resistor according to smbus specification. 22 scl smbus clock i/o. connect to the clock line from the host controller or smart battery. connect a 10k pull-up resistor according to smbus specification. 23 prochot# open-drain output. pulled low when achot, dchot or low_vsys is detected. imvp-8 compliant. smbus command to pull low with otgcurrent, bagone, acok, an d general purpose comparator (refer to table 15 on page 28 ). 24 acok adapter presence indicator output to indicate the adapter is ready. 25 batgone input pin to the ic. logic high on this pin indicates the battery has been removed. logic low on this pin indicates th e battery is present. batgone pin logic high will force bgate fet to turn-off in any circumstances. 26 otgpg/ cmout open-drain output. otg function output power-good indicator or the stand-alone comparator output. when otg function is enabled, low if otg outp ut voltage is not within regulation window. when otg function is not used, it is the general purpose comparator output. 27 prog a resistor from prog pin to gnd sets the following configurations: 1. default number of the battery cells in series, 1-, 2-, 3-, or 4-cell. 2. default switching frequency 733khz or 1mhz. 3. default adapter current limit value 0.476a or 1.5a. 4. autonomous charging mode enable or disable refer to table 23 for programming options. 28 comp error amplifier output. connect a compensa tion network externally from comp to gnd. 29 amon/ bmon adapter current, otg output current, battery charging current, or battery discharging current monitor output. v amon = 18x(v csip -v csin ) for adapter current monitor v otgcmon = 18x(v csin -v csip ) for otg output current monitor v bmon_discharging = 18x(v cson -v csop ) for battery discharging current monitor v bmon_charging = 36x(v csop -v cson ) for battery charging current monitor 30 psys current source output that indicates the whole platform power consumption. psys gain = 1.44a/w (default) or 0.723a/w 31 vbat battery voltage sensing. used for trickle charging dete ction and ideal diode mode control. connect to >1f ceramic capacitor from vbat pin to gnd. vbat pin is also one of the two internal low power ldo inputs. 32 bgate gate drive output to the p-channel fet connecting the syst em and the battery. this pin can go high to disconnect the battery, low to connect the battery or operate in a linear mo de to regulate trickle charge current during trickle charge. when bgate turns on, it is clamped 10v below vsys pin voltage. pin descriptions pin number pin name description ISL9238, ISL9238a 6 fn8877.2 november 9, 2016 submit document feedback block diagram figure 2. block diagram prog scl smbus/i 2 c digital control and fuse logi c dac and cntl logi c for oc/ ov/uv/ ot 5v ldo bgat e logic dr iver buck/boost pwm modu lator and driver drv 0.8v cson csop amon/ bmon csin csip vdd sda dcin acok acin boot1 ugate1 phase1 lgate1 gnd lgate2 vddp phase2 ugate2 boot2 comp vsys bgate 18 x + _ 18 x drv prochot# buf otgpg/cmout vbat asgate drv adp loop se lector error amp lifier batgone 18 x 36 x bmon amon csip low pwr ldo vbat cmp cmp 1.2v/2v o tge n/cmin otgdac otg cont rol tr ickl e cont rol cmp 3.2v cmp cmp 3.8v 2.7v otgdac csip cmp cmp 2.4v 5.2v 5p2 5p2 + + - - + + - - + + - + - - + + - - + + + - - - - - + + + + - - psys mult acfb ccfb vadp vbat vsys vsysdac acdac acfb ccdac ccfb csip vindac ISL9238, ISL9238a 7 fn8877.2 november 9, 2016 submit document feedback simplified application circuit figure 3. simplified application diagram ISL9238, ISL9238a vbat csop cson psys bgate asgate prochot# acin acok gnd csip csin amon/bmon batgone vadp vbat vsys 20m vsys vadp vsys otgpg/cmout adp otgen/cmin q1 q2 q4 q3 10m r s1 r s2 l1 boot1 phase1 ugate1 lgate1 lgate2 ugate2 phase2 boot2 vddp scl sda dcin vdd comp prog ISL9238, ISL9238a 8 fn8877.2 november 9, 2016 submit document feedback absolute maximum rating s thermal information csip, csin, dcin, adp, asgate . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v phase1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(gnd - 0.3v) to +28v phase1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-2v(<20ns) to +28v boot1, ugate1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(gnd - 0.3v) to +33v phase2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(gnd - 0.3v) to +24v phase2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 2v(<20ns) to +24v boot2, ugate2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(gnd - 0.3v) to +29v lgate1, lgate2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (gnd - 0.3v) to +6.5v lgate1, lgate2 . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 2v(<20ns) to +6.5v vbat, vsys, csop, cson, bgate . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +24v vdd, vddp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v amon/bmon, psys. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v otgen, batgone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v acin, acok, prochot#, otgpg . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v clk, dat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v boot1-phase1, boot2-phase2 . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v csip-csin, csop-cson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +0.5v vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ma acin, sda, scl, dcin, acok. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ma esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101a) . . . . . . . . . . . . . 1kv latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jb (c/w) 32 ld tqfn package ( notes 6 , 7 ) . . . . . . . 37 2 ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . .-10c to +100c junction temperature range (t j ) . . . . . . . . . . . . . . . . . . . .-10c to +125c storage temperature range (t s ) . . . . . . . . . . . . . . . . . . . .-65c to +175c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature hrtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c irtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +125c adapter voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4v to +23v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 7. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: adp = csip = csin = 5v and 20v, v sys = v bat = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperatur e range, -10c to +125c unless otherwise specified . parameter symbol test conditions min ( note 8 )typ max ( note 8 )unit uvlo/acok vadp uvlo rising vadp_uvlo_r 3.1 3.3 3.5 v vadp uvlo hysteresis vadp_uvlo_h 600 mv v bat uvlo rising vbat_uvlo_r 2.30 2.45 2.65 v v bat uvlo hysteresis vbat_uvlo_h 400 mv v bat 5p2v rising vbat_5p2_r 5.05 5.20 5.65 v v bat 5p2v hysteresis vbat_5p2_h 490 mv vdd 2p7 por falling, smbus and bgate/bmon active threshold vdd_2p7_f 2.50 2.70 2.9 v vdd 2p7 por hysteresis vdd_2p7_h 150 mv vdd 3p8 por rising, modulator and gate driver active vdd_3p8_r 3.6 3.8 3.9 v vdd 3p8 por hysteresis vdd_3p8_h 150 mv acin rising acin_r 0.775 0.800 0.825 v acin hysteresis acin_h 50 mv ISL9238, ISL9238a 9 fn8877.2 november 9, 2016 submit document feedback linear regulator vdd output voltage vdd 6v < v dcin < 23v, no load 4.5 5.0 5.5 v vdd dropout voltage vdd_dp 30ma, v dcin = 4v 85 mv vdd overcurrent threshold vdd_oc hrtz 80 115 150 ma vdd overcurrent threshold irtz 75 115 150 ma battery current i bat1 battery only, bgate on, psys off, bmon off, v bat = 16.8v, dcin current comes from battery, i bat = i vbat + i csop + i cson + i dcin + i vsys 24 50 a i bat2 battery only, bgate on, psys off, bmon on, v bat = 16.8v, dcin current comes from battery, i bat = i vbat + i csop + i cson + i dcin + i vsys 74 a i bat3 battery only, bgate on, psys on, bmon off, v bat = 16.8v, dcin current comes from battery, i bat = i vbat + i csop + i cson + i dcin + i vsys 905 1055 a adapter current regulation, r s1 = 20m adapter current accuracy csip-csin = 80mv 4 a -2 2 % csip-csin = 40mv 2 a -2.5 2.5 % csip-csin = 10mv 0.5 a -10 10 % adapter current prochot# threshold r s1 = 20m i adp_hot_th10 acprochot = 0x1580h (5504ma) 5504 ma -1.5 1.5 % acprochot = 0x0a80h (2688ma) 2688 ma -3.0 3.0 % acprochot = 0x0400h (1024ma) 1024 ma -6.0 6.0 % system voltage regulation maximum system voltage accuracy hrtz maxsystemvoltage for 1-cell (4.2v) -0.75 0.75 % maxsystemvoltage for 1-cell (8.4v) -0.6 0.6 % maxsystemvoltage for 3-cell and 4-cell (12.6v and 16.8v) -0.5 0.5 % irtz maxsystemvoltage for 1-cell (4.2v) -0.85 0.85 % maxsystemvoltage for 1-cell (8.4v) -0.7 0.7 % maxsystemvoltage for 3-cell and 4-cell (12.6v and 16.8v) 0.55 0.50 % minimum system voltage accuracy -3 3 % input voltage regulation accuracy 4.096v 3.98 4.22 % electrical specifications operating conditions: adp = csip = csin = 5v and 20v, v sys = v bat = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperatur e range, -10c to +125c unless otherwise specified . (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 )unit ISL9238, ISL9238a 10 fn8877.2 november 9, 2016 submit document feedback charge current regulation, r s2 = 10m (limits apply across temper ature range of 0c to +85c) charge current accuracy csop-cson = 60mv 6.03 a -2 2 % csop-cson = 20mv 2.01 a -4 4 % csop-cson = 10mv 1.005 a -5 6 % csop-cson = 5mv 0.501 a -10 12 % bgate clamp vsys-vbgate on charging enabled 6.80 8.30 9.16 v vsys-vbgate off charging disabled 0 v asgate clamp vadp-vasgate on 12 v vsys-vbgate off 0v trickle charging current regulation, r s2 = 10m (limits apply across temper ature range of 0c to +85c) trickle charge current accuracy trickle, options 512ma 410 512 614 ma trickle, options 256ma 205 256 334 ma trickle, 128ma 77 128 192 ma trickle, 64ma 16 64 128 ma fast charge to trickle charge threshold v sys - v bgate 4.23 5.18 5.97 v trickle charge to fast charge threshold hysteresis v sys - v bgate 55 130 210 mv fast charge to trickle charge bgate threshold v sys > 7v, v fb >> v ref 1.15 v trickle charge to fast charge bgate threshold hysteresis v sys > 7v, v fb >> v ref 50 mv ideal diode mode entering ideal diode mode vsys voltage threshold bgate off, vsys falling v vbat - v vsys 100 150 200 mv exiting ideal diode mode battery discharging current threshold r s2 = 10m 110 200 290 ma exiting ideal diode mode battery charging current threshold r s2 = 10m 50 130 200 ma bgate source vsys - bgate = 2v, charging disabled 4 6 10 ma bgate sink bgate - gnd = 2v, charging enabled 20 30 40 a bgate sink bgate - gnd = 2v, in ideal diode mode 6 a amon/bmon input current sense amplifier, r s1 = 20m csip/csin input voltage range v csip/n 423 v/v amon gain 17.97 v/v amon accuracy v amon = 17.9 * (csip - csin) v csip - v csin = 100mv (5a), csip = 5v - 20v -2 2 % v csip - v csin = 20mv (1a), csip = 5v - 20v -5 5 % v csip - v csin = 10mv (0.5a), csip = 5v - 20v -10 10 % v csip - v csin = 2mv (0.1a), csip = 5v - 20v -40 40 % electrical specifications operating conditions: adp = csip = csin = 5v and 20v, v sys = v bat = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperatur e range, -10c to +125c unless otherwise specified . (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 )unit ISL9238, ISL9238a 11 fn8877.2 november 9, 2016 submit document feedback reverse amon gain 17.9 v/v amon accuracy v amon = 17.9 * (csin - csip) v csin - v csip = 80mv (4a), csip = 4v - 22v -2.5 2.5 % v csin - v csip = 20mv (1a), csip = 4v - 22v -6.5 4.5 % v csin - v csip = 10mv (0.5a), csip = 4v - 22v -12 9 % v csin - v csip = 5.12mv (0.256a), csip = 4v - 22v -25 25 % amon minimum output voltage v csip - v csin = 0v 30 mv discharge current sense amplifier, r s2 = 10m bmon gain (battery discharging) 17.78 v/v bmon accuracy v bmon = 17.9 * (v cson - v csop ) v cson - v csop = 100mv (10a), v cson = 8v -2 2 % v cson - v csop = 20mv (2a), v cson = 8v -7.0 -1.5 3.0 % v cson - v csop = 10mv (1a), v cson = 8v -10.5 -2.5 5.5 % v cson - v csop = 6mv (0.6a), v cson = 8v -17 -4 12 % bmon gain (battery charging) limits apply across temperature range of 0c to +85c 35.7 v/v bmon accuracy v bmon = 35.7* (v cson - v csop ) v csop - v cson = 60mv (6a), v cson = 8v -3 3 % v csop - v cson = 40mv (4a), v cson = 8v -4 4 % v csop - v cson = 10mv (1a), v cson = 8v -10 10 % v csop - v cson = 5mv (0.5a), v cson = 8v -25 25 % bmon minimum output voltage v csop - v cson = 0v 30 mv discharging current prochot# threshold, r s2 = 10m i dis_hot_th dcprochot = 2.048a 1.77 2.08 2.39 a discharging current prochot# threshold, battery only, r s2 = 10m i dis_hot_th dcprochot = 12a 10.8 13.5 17 a dcprochot = 6a 5.35 6.5 8 a amon/bmon source resistance ( note 9 ) 5 amon/bmon sink resistance ( note 9 ) 5 batgone and otgen high-level input voltage 0.9 v low-level input voltage 0.4 v input leakage current v batgone = 3.3v, 5v; v otgen = 3.3v, 5v 1 a prochot# prochot# debounce time prochot# debounce register bit<1:0> = 11 0.85 1 1.15 ms prochot# debounce register bit<1:0> = 10 425 500 575 s prochot# duration time prochot# du ration register bit<2:0> = 011 8.5 10 11.5 ms prochot# duration register bit<2:0> = 001 17 20 23 ms low vsys prochot# trip threshold v low_vsys_hot control1 register bit<1:0> = 00 5.8 6.0 6.2 v control1 register bit<1:0> = 01 6.1 6.3 6.5 v control1 register bit<1:0> = 10 6.4 6.6 6.8 v control1 register bit<1:0> = 11 6.7 6.9 7.1 v electrical specifications operating conditions: adp = csip = csin = 5v and 20v, v sys = v bat = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperatur e range, -10c to +125c unless otherwise specified . (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 )unit ISL9238, ISL9238a 12 fn8877.2 november 9, 2016 submit document feedback psys psys output current r s1 = 20m r s2 = 10m i psys = 1.493 x power + 1.43a i psys control3 bit<9> = 1 v csip = 19v, v csip-csin = 80mv, v bat = 12v, v csop-cson = 10mv -5 5 % v csip = 19v, v csip-csin = 80mv, v bat = 12v, v csop-cson = -10mv -5.3 5.3 % i psys control3 bit<9> = 0 v csip = 19v, v csip-csin = 0mv, v bat = 8.4v, v csop-cson = 20mv -7 7 % v csip = 19v, v csip-csin = 0mv, v bat = 4.2v, v csop-cson = 10mv -15 15 % maximum psys output voltage v psys_max 4 v otg otg voltage otgvoltage register = 5.12v 4.95 5.03 5.12 v otg current (5v to 12v) otgcurrent register = 512ma 435 512 589 ma otgcurrent register = 1024ma 922 1024 1126 ma otgcurrent register = 4096ma 3975 4096 4240 ma general purpose comparator general purpose comparator rising threshold reference = 1.2v 1.15 1.2 1.25 v reference = 2v 1.95 2 2.05 v general purpose comparator hysteresis reference = 1.2v 30 60 90 mv reference = 2v 30 60 90 mv protection vsys overvoltage rising threshold maxsystemvoltage register value = 8.4v 8.95 9.15 9.35 v vsys overvoltage hysteresis 250 400 550 mv adapter way overcurrent rising threshold ( note 9 ) r s1 = 20m 7.5 12 18 a adapter way overcurrent hysteresis 5 6.6 8 a battery discharge way overcurrent rising threshold ( note 9 ) r s2 = 10m 10 20 32 a battery discharge way overcurrent hysteresis ( note 9 ) 7.5 9 10.5 a over-temperature threshold ( note 9 ) 140 150 160 c adapter overvoltage rising threshold 22.5 23.4 24 v adapter overvoltage hysteresis 150 350 500 mv otg undervoltage falling threshold otg voltage = 5.004v 3.45 3.80 4.25 v otg overvoltage rising threshold otg voltage = 5.004v 5.8 6.2 6.6 v electrical specifications operating conditions: adp = csip = csin = 5v and 20v, v sys = v bat = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperatur e range, -10c to +125c unless otherwise specified . (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 )unit ISL9238, ISL9238a 13 fn8877.2 november 9, 2016 submit document feedback oscillator oscillator frequency. digital core only 0.85 1 1.15 mhz digital debounce time accuracy ( note 9 ) -15 15 % miscellaneous switching frequency accuracy comp>1.7v and not in period stretching -15 15 % battery learn mode auto-exit threshold minsystemvoltage = 5.376v control1 register bit<13> = 1 5.05 5.35 5.7 v battery learn mode auto-exit hysteresis ( note 9 ) 180 330 480 mv smbus sda/scl input low voltage 3.3v 0.8 v sda/scl input high voltage 3.3v 2 v sda/scl input bias current 3.3v 1 a sda, output sink current sda = 0.4v, on 4 ma smbus frequency f smb 10 400 khz gate driver ugate1 pull-up resistance ug1 rpu 100ma source current 800 1200 ? m ugate1 source current ug1 src ugate1 - phase1 = 2.5v 1.3 2a ugate1 pull-down resistance ug1 rpd 100ma sink current 350 475 m ugate1 sink current ug1 snk ugate1 - phase1 = 2.5v 1.9 2.8 a lgate1 pull-up resistance lg1 rpu 100ma source current 800 1200 m lgate1 source current lg1 src lgate1 - gnd = 2.5v 1.3 2a lgate1 pull-down resistance lg1 rpd 100ma sink current 300 450 m lgate1 sink current lg1 snk lgate1 - gnd = 2.5v 2.3 3.5 ? a lgate2 pull-up resistance lg2 rpu 100ma source current 800 1200 ? m lgate2 source current lg2 src lgate2 - gnd = 2.5v 1.3 2a lgate2 pull-down resistance lg2 rpd 100ma sink current 300 450 m lgate2 sink current lg2 snk lgate2 - gnd = 2.5v 2.3 3.5 a ugate2 pull-up resistance ug2 rpu 100ma source current 800 1200 m ugate2 source current ug2 src ugate2 - phase2 = 2.5v 1.3 2a ugate2 pull-down resistance ug2 rpd 100ma sink current 300 450 m ugate2 sink current ug2 snk ugate2 - phase2 = 2.5v 2.3 3.5 ? a ugate1 to lgate1 dead time t ug1lg1dead 10 20 40 ns lgate1 to ugate1 dead time t lg1ug1dead 10 20 40 ns lgate2 to ugate2 dead time t lg2ug2dead 10 20 40 ns ugate2 to lgate2 dead time t ug2lg2dead 10 20 40 ns electrical specifications operating conditions: adp = csip = csin = 5v and 20v, v sys = v bat = csop = cson = 8v, unless otherwise noted. boldface limits apply across the junction temperatur e range, -10c to +125c unless otherwise specified . (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 )unit ISL9238, ISL9238a 14 fn8877.2 november 9, 2016 submit document feedback smbus timing specification ( note 9 ) parameters symbol test conditions min ( note 8 )typ max ( note 8 )unit smbus frequency f smb 10 400 khz bus free time t buf 4.7 s start condition hold time from scl t hd:sta 4 s start condition set-up time from scl t su:sta 4.7 s stop condition set-up time from scl t su:sto 4 s sda hold time from scl t hd:dat 300 ns sda set-up time from scl t su:dat 250 ns scl low period t low 4.7 s scl high period t high 4 s smbus inactivity timeout maximum charging period without a smbus write to maxsystemvoltage or chargecurrent register 175 s notes: 8. parameters with min and/or ma x limits are 100% tested at +25c, unless otherw ise specified. temperatur e limits established by characterization and are not production tested. 9. limits established by characteriza tion and are not production tested. gate driver timing diagram figure 4. gate driver timing diagram pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr ISL9238, ISL9238a 15 fn8877.2 november 9, 2016 submit document feedback typical performance figure 5. adapter insertion, v adp = 2ov, v bat = 11v, chargecurrent = 0a figure 6. adapter insertion, v adp = 2ov, v bat = 11v, chargecurrent = 0a ( figure 5 zoom in) figure 7. adapter removal, v adp = 2ov, v bat = 11v, chargecurrent = 0a figure 8. adapter voltage ramps up, boost -> buck-boost -> buck operation mode transition figure 9. adapter voltage ramps down, buck -> buck-boost -> boost operation mode transition ISL9238, ISL9238a 16 fn8877.2 november 9, 2016 submit document feedback figure 10. boost mode, output voltage loop to adapter current loop transition. v adp = 5v, maxsystemvoltage = 12.576v, v bat = 11v, system load 0.5a to 10a step, adaptercurrentlimit = 3a, chargecurrent = 0a figure 11. boost mode, charging current loop to adapter current loop transition. v adp = 5v, maxsystemvoltage = 12.5766v, v bat = 11v, system load 0.5a to 10a step, adaptercurrentlimit = 3a, chargecurrent = 1a figure 12. buck-boost mode, output voltage loop to adapter current loop transition. v adp = 12v, maxsystemvoltage = 12.576v, v bat = 11v, system load 1a to 10a step, adaptercurrentlimit = 3a, chargecurrent = 0a figure 13. buck-boost mode, charging current loop to adapter current loop transition. v adp = 12v, maxsystemvoltage = 12.576v, v bat = 11v, system load 1a to 10a step, adaptercurrentlimit = 3a, chargecurrent = 1a typical performance (continued) ISL9238, ISL9238a 17 fn8877.2 november 9, 2016 submit document feedback figure 14. buck mode, output voltage loop to adapter current loop transition. v adp = 20v, maxsystemvoltage = 12.576v, v bat = 11v, system load 2a to 10a step, adaptercurrentlimit = 3a, chargecurrent = 0a figure 15. buck mode, charging current loop to adapter current loop transition. v adp = 20v, maxsystemvoltage = 12.576v, v bat = 11v, system load 2a to 10a step, adaptercurrentlimit = 3a, chargecurrent = 3a figure 16. boost mode, output voltage loop to input voltage loop transition. v adp = 5.004v, maxsystemvoltage = 12.576v, v bat = 11v, vindac = 4.437v, system load 0a to 10a step, chargecurrent = 0a figure 17. boost mode, charging current loop to input voltage loop transition. v adp = 5.004v, maxsystemvoltage = 12.576v, v bat = 11v, vindac = 4.437v, system load 0a to 10a step, chargecurrent = 0.5a typical performance (continued) ISL9238, ISL9238a 18 fn8877.2 november 9, 2016 submit document feedback general smbus architecture data validity the data on the sda line must be stable during the high period of the scl, unless generating a start or stop condition. the high or low state of the data line can only change when the clock signal on the scl line is low. refer to figure 21 . start and stop conditions figure 22 start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition on the sda line while scl is high. a stop condition must be sent before each start condition. acknowledge each address and data transmission uses 9 clock pulses. the ninth pulse is the acknowledge bit (ack). after the start condition, the master sends 7 slave address bits and a r/w bit during the next 8 clock pulses. during the 9th clock pulse, the device that recognizes its own address holds the data line low to acknowledge (refer to figure 23 ). the acknowledge bit is also used by both the master and the slave to acknowledge receipt of register addresses and data. figure 18. otg mode enable, otg enable 150ms debounce time figure 19. otg mode 0.5a to 2a transient load, otg voltage = 5.12v typical performance (continued) figure 20. general smbus architecture scl control output sda control output input input state machine registers memory etc... smbus slave scl control output sda control output input input state machine registers memory etc... smbus slave scl control output sda control output input input cpu smbus master to other slave devices vdd smb scl sda figure 21. data validity sda scl data line stable data valid change of data allowed figure 22. start and stop waveforms sda scl s start condition p stop condition ISL9238, ISL9238a 19 fn8877.2 november 9, 2016 submit document feedback smbus transactions all transactions start with a control byte sent from the smbus master device. the control byte begins with a start condition, followed by 7 bits of slave address (0001001 for the ISL9238 and 0001101 for the ISL9238a) and the r/w bit. the r/w bit is 0 for a write or 1 for a read. if any slave device on the smbus bus recognizes its ad dress, it will acknowledge by pulling the serial data (sda) line low for the last clock cycle in the control byte. if no slave exists at that address or it is not ready to communicate, the data line will be one, indicating a not acknowledge condition. once the control byte is sent and the ISL9238 and ISL9238a acknowledges it, the second byte sent by the master must be a register address byte such as 0x14 for the chargecurrent register. the register addre ss byte tells the ISL9238 and ISL9238a which register the master will write or read. see table 2 on page 20 for details of the registers. once the ISL9238 and ISL9238a receives a register address byte, it will respond with an acknowledge. byte format every byte put on the sda line must be 8 bits long and must be followed by an acknowledge bit. data is transferred with the most significant bit first (msb) and the least significant bit last (lsb). the lo byte data is transferred before the hi byte data. for example, when writing 0x41a0, 0xa0 is written first and 0x41 is written second. smbus and i 2 c compatibility the ISL9238 and ISL9238a smbu s minimum input logic high voltage is 2v, so it is compatible with i 2 c with higher than 2v pull-up power supply. the ISL9238 and ISL9238a smbus registers are 16 bits, so it is compatible with 16 bits i 2 c or 8 bits i 2 c with auto-increment capability. ISL9238 and ISL9238a smbus commands the ISL9238 and ISL9238a receives control inputs from the smbus interface after power-on reset (por ). the serial interface complies with the system management bus specification, which can be downloaded from www.smbus.org . the ISL9238 and ISL9238a uses the smbus read-word and write-word protocols (see figure 24 ) to communicate with the host system and a smart battery. the ISL9238 and ISL9238a is an smbus slave device and does not initiate communication on the bus. it responds to the 7-bit address 0b0001001_(ISL9238) /0b0001101_(isl9 238a) as follows: read and write address for ISL9238/ISL9238a is read address = 0b00010011 (0x13h)/0b00011011 (0x1bh) write address = 0b00010010 (0x12h)/0b00011010 (0x1ah) the data (sda) and clock (scl) pi ns have schmitt-trigger inputs that can accommodate slow edges. choose pull-up resistors for sda and scl to achieve rise times according to the smbus specifications. the illustration in this datashee t is based on current sensing resistors r s1 = 20m ? and r s2 = 10m unless otherwise specified. figure 23. acknowledge on the smbus sda scl start acknowledge from slave 12 89 msb s slave addr + w a register addr a lo byte data a hi byte data a p write to a register s slave addr + w a register addr a read from a register p s slave addr + r a lo byte data a hi byte data n p s start p stop a acknowledge n no acknowledge driven by the master p driven by the ic ISL9238, ISL9238a 20 fn8877.2 november 9, 2016 submit document feedback table 2. register summary register names register address read/ write number of bits description default chargecurrentlimit 0x14 r/w 11 [12:2]11-bit, lsb size 4ma, total range 6080ma with 10m r s2 0a maxsystemvoltage 0x15 r/w 12 [14:3]12-bit, lsb size 8mv, total range 18.304v 4.192v for 1-cell 8.384v for 2-cell 12.576v for 3-cell 16.768v for 4-cell t1 and t2 0x38 r/w 6 configure two-level adapter current limit duration 0x000h control0 0x39 r/w 16 configure various charger options 0x0000h information1 0x3a r 16 indicate various charger status 0x0000h adaptercurrentlimit2 0x3b r/w 11 [12:2]11-bit, lsb size 4ma, total range 6080ma with 20m r s1 1500ma control1 0x3c r/w 16 configure various charger options 0x0000h control2 0x3d r/w 16 configure various charger options 0x0000h minsystemvoltage 0x3e r/w 6 [13:8]6-bit, lsb size 256mv, total range 13.824v 2.56v for 1-cell 5.12v for 2-cell 7.68v for 3-cell 10.24v for 4-cell adaptercurrentlimit1 0x3f r/w 11 [12:2]11-bit, lsb size 4ma, total range 6080ma with 20m r s1 set by prog pin acprochot# 0x47 r/w 6 [12:7] adapter current prochot# threshold default 3.072a, 128ma resolution for 20m r s1 . 3.072a dcprochot# 0x48 r/w 6 [13:8] battery discharging current prochot# threshold default 4.096a, 256ma resolution for 10m r s2 . 4.096a otg voltage 0x49 r/w 12 [14:3] 12-bit, lsb size 12mv, total range 27.456v otg mode voltage reference 5.004v otg current 0x4a r/w 6 [12:7] 6-bit, lsb size 128mav, total range 4.096a otg mode maximum current limit 0.512a v in voltage 0x4b r/w 6 [13:8] 6-bit, lsb size 341.3mv, total range 18.432mv v in loop voltage reference 4.096v control3 0x4c r/w 16 configure various charger options 0x0000h information2 0x4d r 16 indicate various charger status 0x0000h control4 0x4e r/w 8 [7:0] 8-bit, configure various charger options 0x0000h manufacturer id 0xfe r 8 manufacturers id register ? 0x49 - read only 0x0049h device id 0xff r 8 device id regi ster - 0x0c- read only 0x000ch ISL9238, ISL9238a 21 fn8877.2 november 9, 2016 submit document feedback setting charging current limit to set the charging current limit, write a 16-bit chargecurrentlimit command (0x14h or 0b00010100) using the write-word protocol shown in figure 24 on page 19 and the data format shown in table 3 for a 10m r s2 or table 4 for a 5m r s2 . the ISL9238 and ISL9238a limits the charging current by limiting the csop-cson voltage. by usin g the recommended current sense resistor values r s1 = 20m ? and r s2 = 10m , the register?s lsb always translates to 4ma of charging current. the chargecurrentlimit register accepts any charging current command but only the valid register bits will be written to the register and the maximum values is clamped at 6080ma for r s2 =10m . after por, the chargecurrentlimit register is reset to 0x0000h. to set the battery charging current va lue, write a non-zero number to the chargecurrentlimit register. the chargecurrentlimit register can be read back to verify its content. table 24 shows the conditions to enable fast charging according to the chargecurrentlimit register setting. setting adapter current limit to set the adapter current limit, write a 16-bit adaptercurrentlimit1 command (0x3fh or 0b00111111) and/or adaptercurrentlimit2 command (0x3bh or 0b00111011) using the write-word protocol shown in figure 24 on page 19 and the data format shown in table 5 on page 22 for a 20m r s1 or table 6 on page 22 for a 10m r s1 . the ISL9238 and ISL9238a limits the adapter current by limiting the csip-csin voltage. by usin g the recommended current sense resistor values, the register?s lsb always translates to 4ma of adapter current. any adapter current limit command will be accepted but only the valid register bits will be written to the adaptercurrentlimit1 and adapterc urrentlimit2 registers and the maximum values is clamped at 6080ma for r s1 = 20m . after adapter por, the adaptercurrentlimit1 register is reset to the value programmed through the prog pin resistor. the adaptercurrentlimit2 register is se t to its default value of 1.5a or keep the value that is written to it previously if battery is present first. the adaptercurrentlimit1 and adaptercurrentlimit2 registers can be read back to verify their content. to set a second level adapter current limit, write a 16-bit adaptercurrentlimit2 (0x3bh or 0b00111011) command using the write-word protocol shown in figure 24 and the data format as shown in table 5 for a 20m r s1 or table 6 for a 10m r s1 . table 3. chargecurrentlimit register 0x14h (11-bit, 4ma step, 10m sense resistor, x36) bit description <1:0> not used <2> 0 = add 0ma of charge current limit. 1 = add 4ma of charge current limit. <3> 0 = add 0ma of charge current limit. 1 = add 8ma of charge current limit. <4> 0 = add 0ma of charge current limit. 1 = add 16ma of charge current limit. <5> 0 = add 0ma of charge current limit. 1 = add 32ma of charge current limit. <6> 0 = add 0ma of charge current limit. 1 = add 64ma of charge current limit. <7> 0 = add 0ma of charge current limit. 1 = add 128ma of charge current limit. <8> 0 = add 0ma of charge current limit. 1 = add 256ma of charge current limit. <9> 0 = add 0ma of charge current limit. 1 = add 512ma of charge current limit. <10> 0 = add 0ma of charge current limit. 1 = add 1024ma of charge current limit. <11> 0 = add 0ma of charge current limit. 1 = add 2048ma of charge current limit. <12> 0 = add 0ma of charge current limit. 1 = add 4096ma of charge current limit. <13:15> not used maximum <12:2> = 10111110000 6080ma table 4. chargecurrentlimit register 0x14h (11-bit, 8ma step, 5m sense resistor, x36) bit description <1:0> not used <2> 0 = add 0ma of charge current limit. 1 = add 8ma of charge current limit. <3> 0 = add 0ma of charge current limit. 1 = add 16ma of charge current limit. <4> 0 = add 0ma of charge current limit. 1 = add 32ma of charge current limit. <5> 0 = add 0ma of charge current limit. 1 = add 64ma of charge current limit. <6> 0 = add 0ma of charge current limit. 1 = add 128ma of charge current limit. <7> 0 = add 0ma of charge current limit. 1 = add 256ma of charge current limit. <8> 0 = add 0ma of charge current limit. 1 = add 512ma of charge current limit. <9> 0 = add 0ma of charge current limit. 1 = add 1024ma of charge current limit. <10> 0 = add 0ma of charge current limit. 1 = add 2048ma of charge current limit. <11> 0 = add 0ma of charge current limit. 1 = add 4096ma of charge current limit. <12> 0 = add 0ma of charge current limit. 1 = add 8192ma of charge current limit. <13:15> not used maximum <12:2> = 10111110000 12160ma ISL9238, ISL9238a 22 fn8877.2 november 9, 2016 submit document feedback the adaptercurrentlimit2 register has the same specification as the adaptercurrentlimit1 register. refer to ? two-level adapter current limit ? on page 36 for detailed operation. setting two-level adapter current limit duration for a two-level adapter current limit, write a 16-bit t1 and t2 command (0x38h or 0b00111000) using the write-word protocol shown in figure 24 and the data format shown in table 5 or table 6 to set the adaptercurrentlimit1 duration t1. write a 16-bit t2 command (0x38h or 0b00111000) to set adaptercurrentlimit2 duration t2. t1 and t2 register accepts any command but only the valid register bits will be written. refer to ? two-level adapter current limit ? on page 36 for detailed operation. table 5. adaptercurrentlimit1 register 0x3fh and adaptercurrentlimit2 register 0x3bh (11-bit, 4ma step, 20m sense resistor, x18) bit description <1:0> not used <2> 0 = add 0ma of adapter current limit. 1 = add 4ma of adapter current limit. <3> 0 = add 0ma of adapter current limit. 1 = add 8ma of adapter current limit. <4> 0 = add 0ma of adapter current limit. 1 = add 16ma of adapter current limit. <5> 0 = add 0ma of adapter current limit. 1 = add 32ma of adapter current limit. <6> 0 = add 0ma of adapter current limit. 1 = add 64ma of adapter current limit. <7> 0 = add 0ma of adapter current limit. 1 = add 128ma of adapter current limit. <8> 0 = add 0ma of adapter current limit. 1 = add 256ma of adapter current limit. <9> 0 = add 0ma of adapter current limit. 1 = add 512ma of adapter current limit. <10> 0 = add 0ma of adapter current limit. 1 = add 1024ma of adapter current limit. <11> 0 = add 0ma of adapter current limit. 1 = add 2048ma of adap ter current limit. <12> 0 = add 0ma of adapter current limit. 1 = add 4096ma of adap ter current limit. <13:15> not used maximum <12:4> = 10111110000 6080ma table 6. adaptercurrentlimit1 register 0x3fh and adaptercurrentlimit2 register 0x3bh (11-bit, 8ma step, 10m sense resistor, x18) bit description <1:0> not used. <2> 0 = add 0ma of adapter current limit. 1 = add 8ma of adapter current limit. <3> 0 = add 0ma of adapter current limit. 1 = add 16ma of adapter current limit. <4> 0 = add 0ma of adapter current limit. 1 = add 32ma of adapter current limit. <5> 0 = add 0ma of adapter current limit. 1 = add 64ma of adapter current limit. <6> 0 = add 0ma of adapter current limit. 1 = add 128ma of adapter current limit. <7> 0 = add 0ma of adapter current limit. 1 = add 256ma of adapter current limit. <8> 0 = add 0ma of adapter current limit. 1 = add 512ma of adapter current limit. <9> 0 = add 0ma of adapter current limit. 1 = add 1024ma of adapter current limit. <10> 0 = add 0ma of adapter current limit. 1 = add 2048ma of adapter current limit. <11> 0 = add 0ma of adapter current limit. 1 = add 4096ma of adapter current limit. <12> 0 = add 0ma of adapter current limit. 1 = add 8192ma of adapter current limit. <13:15> not used maximum <12:4> = 10111110000 12160ma table 7. t1 and t2 register 0x38h bit description <2:0> t1 000 = 10ms (default) 001 = 20ms 010 = 15ms 011 = 5ms 100 = 1ms 101 = 0.5ms 110 = 0.1ms 111 = 0ms <7:3> not used <10:8> t2 000 = 10s (default) 001 = 100s 010 = 500s 011 = 1ms 100 = 300s 101 = 750s 110 = 2ms 111 = 10ms <15:11> not used table 6. adaptercurrentlimit1 register 0x3fh and adaptercurrentlimit2 register 0x3bh (11-bit, 8ma step, 10m sense resistor, x18) (continued) bit description ISL9238, ISL9238a 23 fn8877.2 november 9, 2016 submit document feedback setting maximum charging voltage or system regulating voltage to set the maximum charging voltage or the system regulating voltage, write a 16-bit maxsys temvoltage command (0x15h or 0b00010101) using the write-word protocol shown in figure 24 on page 19 and the data format as shown in table 8 . the maximum system voltage range is 8mv to 18.304v. the maxsystemvoltage register accepts any voltage command but only the valid register bits will be written to the register and the maximum values is clamped at 18.304v. ISL9238 and ISL9238a accepts 0v command, but register value does not change. the maxsystemvoltage register se ts the battery full charging voltage limit. the maxsystemvoltage register setting also is the system bus voltage regulation point when battery is absent or battery is present but is not in charging mode. see ? system voltage regulation ? on page 37 for details. the vsys pin is used to sense the battery voltage for maximum charging voltage regulation. the vs ys pin is also the system bus voltage regulation sense point. setting minimum system voltage to set the minimum system voltage, write a 16-bit minsystemvoltage command (0x3eh or 0b00111110) using the write-word protocol shown in figure 24 on page 19 and the data format as shown in table 9 . the minimum system voltage range is 256mv to 13.824v. the minsystemvoltage register accepts any voltage command but only the valid register bits will be written to the register. the minsystemvoltage register value should be set lower than the maxsystemvoltage register va lue and the maximum value is clamped at 13.824v. the minsystemvoltage register sets the battery voltage threshold for entry and exit of the trickle charging mode and for entry and exit of the learn mode. the vbat pin is used to sense the battery voltage to compare with the mins ystemvoltage register setting. refer to ? trickle charging ? on page 37 and ? battery learn mode ? on page 36 for details. the minsystemvoltage register sett ing also is the system voltage regulation point when it is in trickle charging mode. the cson pin is the system voltage regulation sense point in trickle charging mode. refer to ? system voltage regulation ? on page 37 ? for details. setting prochot# threshold for adapter overcurrent condition to set the prochot# assertion threshold for adapter overcurrent condition, write a 16-bit acprochot# command (0x47h or 0b01000111) using the write-word protocol shown in table 24 on page 19 and the data format shown in table 10 on page 24 . by using the recommended current sense resistor values, the register?s lsb always translates to 128ma of adapter current. the acprochot# register accepts an y current command but only the valid register bits will be written to the register and the maximum value is clamped at 6400ma for r s1 = 20m . after por, the acprochot# register is reset to 0x0c00h. the acprochot# register can be read back to verify its content. table 8. maxsystemvoltage register 0x15h (8mv step) bit description <2:0> not used <3> 0 = add 0mv of charge voltage. 1 = add 8mv of charge voltage. <4> 0 = add 0mv of charge voltage. 1 = add 16mv of charge voltage. <5> 0 = add 0mv of charge voltage. 1 = add 32mv of charge voltage. <6> 0 = add 0mv of charge voltage. 1 = add 64mv of charge voltage. <7> 0 = add 0mv of charge voltage. 1 = add 128mv of charge voltage. <8> 0 = add 0mv of charge voltage. 1 = add 256mv of charge voltage. <9> 0 = add 0mv of charge voltage. 1 = add 512mv of charge voltage. <10> 0 = add 0mv of charge voltage. 1 = add 1024mv of charge voltage. <11> 0 = add 0mv of charge voltage. 1 = add 2046mv of charge voltage. <12> 0 = add 0mv of charge voltage. 1 = add 4096mv of charge voltage. <13> 0 = add 0mv of charge voltage. 1 = add 8192mv of charge voltage. <14> 0 = add 0mv of charge voltage. 1 = add 16384mv of charge voltage. <15> not used maximum 18304mv table 9. minsystemvoltage register 0x3eh bit description <7:0> not used <8> 0 = add 0mv of charge voltage. 1 = add 256mv of charge voltage. <9> 0 = add 0mv of charge voltage. 1 = add 512mv of charge voltage. <10> 0 = add 0mv of charge voltage. 1 = add 1024mv of charge voltage. <11> 0 = add 0mv of charge voltage. 1 = add 2046mv of charge voltage. <12> 0 = add 0mv of charge voltage. 1 = add 4096mv of charge voltage. <13> 0 = add 0mv of charge voltage. 1 = add 8192mv of charge voltage. <15:14> not used maximum 13824mv ISL9238, ISL9238a 24 fn8877.2 november 9, 2016 submit document feedback if the adapter current exceeds th e acprochot# register setting, prochot# signal will assert after the debounce time programmed by the control2 register bit<10:9> and latch on for a minimum time programmed by control2 register bit<8:6>. setting prochot# threshold for battery over discharging current condition to set the prochot# signal assertion threshold for battery over discharging current condition, write a 16-bit dcprochot# command (0x48h or 0b01001000) using the write-word protocol shown in figure 24 on page 19 and the data format shown in table 11 . by using the recommended current sense resistor values, the register?s lsb always translates to 256ma of adapter current. the dcprochot# register accepts any current command but only the valid register bits will be written to the register and the maximum values is clamped at 12.8a for r s2 = 10m . after por, the dcprochot# register is reset to 0x1000h. the dcprochot# register can be read back to verify its content. if the battery discharging current exceeds the dcprochot# register setting, the prochot# signal will assert after the debounce time programmed by the control2 register bit<10:9> and latch on for a minimum time programmed by control2 register bit<8:6>. in battery only and low power mode, the dcprochot# threshold is set by control0 register bit<4:3>. in battery only mode, dcprochot# function works only when psys is enabled, since enabling psys will activate the internal comparator reference. the information register bit<15> indicates if the internal comparat or reference is active or not. when the adapter is present, the internal comparator reference is always active. setting prochot# debounce time and duration time control2 register bit<10:9> co nfigures the prochot# signal debounce time before its assertion for acprochot# and dcprochot#. the low system voltage prochot# has a fixed debounce time of 10s. control2 register bit<8:6> configures the minimum duration of prochot# signal once asserted. control registers control0, control1, control2, co ntrol3 and control4 registers configure the operation of the ISL9238 and ISL9238a. to change certain functions or options after por, write an 8-bit control command to control0 register (0x39h or 0b00111001) or a 16-bit control command to control1 register (0x3ch or 0b00111100) or control2 register (0x3dh or 0b00111101) or control3 register (0x4ch or 0b00111100) or control4 register (0x4eh or 0b00111101) using the write-word protocol shown in figure 24 on page 19 and the data format shown in tables 12 , 13 , 14 and 15 on page 16 , respectively. table 10. acprochot# register 0x47h (20m sensing resistor, 128ma step, x18 gain) bit description <6:0> not used <7> 0 = add 0ma of acprochot# threshold. 1 = add 128ma of acprochot# threshold. <8> 0 = add 0ma of acprochot# threshold. 1 = add 256ma of acprochot# threshold. <9> 0 = add 0ma of acprochot# threshold. 1 = add 512ma of acprochot# threshold. <10> 0 = add 0ma of acprochot# threshold. 1 = add 1024ma of acprochot# threshold. <11> 0 = add 0ma of acprochot# threshold. 1 = add 2048ma of acprochot# threshold. <12> 0 = add 0ma of acprochot# threshold. 1 = add 4096ma of acprochot# threshold. <15:13> not used maximum <12:7> = 110010, 6400ma table 11. dcprochot# register 0x48h (10m sensing resistor, 256ma step, x18 gain) bit description <7:0> not used <8> 0 = add 0ma of dcprochot# threshold. 1 = add 256ma of dcprochot# threshold. <9> 0 = add 0ma of dcprochot# threshold. 1 = add 512ma of dcprochot# threshold. <10> 0 = add 0ma of dcprochot# threshold. 1 = add 1024ma of dcprochot# threshold. <11> 0 = add 0ma of dcprochot# threshold. 1 = add 2048ma of dcprochot# threshold. <12> 0 = add 0ma of dcprochot# threshold. 1 = add 4096ma of dcprochot# threshold. <13> 0 = add 0ma of dcprochot# threshold. 1 = add 8192ma of dcprochot# threshold. <15:14> not used. maximum <13:8> = 110010, 12800ma ISL9238, ISL9238a 25 fn8877.2 november 9, 2016 submit document feedback table 12. control0 register 0x39h bit bit name description <15:13> forward buck and buck-boost phase comparator threshold offset bit<15:13> adjusts phase comparator threshol d offset for forward buck and buck-boost 000 = 0mv 001 = 0.5mv 010 = 1mv 011 = 1.5mv 100 = -2mv 101 = -1.5mv 110 = -1mv 111 = -0.5mv <12:10> forward and reverse boost phase comparator threshold offset bit<12:10> adjusts phase comparator thresh old offset for forward and reverse boost 000 = 0mv 001 = 0.5mv 010 = 1mv 011 = 1.5mv 100 = -2mv 101 = -1.5mv 110 = -1mv 111 = -0.5mv <9:8> reverse buck and buck-boost phase comparator threshold offset bit<9:8> adjusts phase comparator threshol d offset for forward and reverse boost 00 = 0mv 01 = 1mv 10 = -2mv 11 = -1mv <7> smbus timeout the ISL9238 and ISL9238a includes a timer to insure the smbus master is active and to prevent overcharging the battery. if the adapter is present and if the ISL9238 and ISL9238a does not receive a write to the maxchargevoltage or chargecurrentlimit regist er within 175s, ISL9238 and ISL9238a will terminate charging. if a timeout occurs, writing the maxchargevol tage or chargecurrentlimit register will re-enable charging. 0 = enable the smbus timeout function. 1 = disable the smbus timeout function. <6:5> high-side fet short detection threshold bit<6:5> configures the high-side fe t short detection phase node voltage threshold during low-side fet turning on. 00 = 400mv (default) 01 = 500mv 10 = 600mv 11 = 800mv <4:3> dcprochot# threshold in battery only low power mode bit<4:3> only configures the battery discharging curre nt dcprochot# threshold in battery only low power mode indicated by the information1 register 0x3a bi t<15>. if psys is enabled, battery discharge current dcprochot# threshold is set by the dcprochot# register 0x48 setting. <2> input voltage regulation loop bit<2> disables or enables the input voltage regulation loop. 0 = enable (default) 1 = disable <1:0> not used bit<4:3> r s2 = 10m (a) r s2 = 20m (a) r s2 = 5m (a) 00 12 (default) 6 24 01 10 5 20 10 8 4 16 11 6 3 12 ISL9238, ISL9238a 26 fn8877.2 november 9, 2016 submit document feedback table 13. control1 register 0x3ch bit bit name description <15:14> general purpose comparator assertion debounce time bit<15:14> configures the general purpose comparator assertio n debounce time. 00 = 2s (default) 01 = 12s 10 = 2ms 11 = 5s 13 exit learn mode option bit<13> provides the option to exit le arn mode when battery voltage is lower than minsystemvoltage register setting. 0 = stay in learn mode even if v bat < minsystemvoltage register setting (default) 1 = exit learn mode if v bat < minsystemvoltage register setting 12 learn mode bit<12> enables or disables the battery learn mode. 0 = disable (default) 1 = enable to enter learn mode, batgone pin needs to be low, i.e., battery must be present. 11 otg function bit<11> enables or disables otg function. 0 = disable (default) 1 = enable 10 audio filter bit<10> enables or disables the audio filter function. 0 = disable (default) 1 = enable <9:8> switching frequency bit<9:8> configures the switching freque ncy and overrides the switching frequency set by prog pin. 00 = switching frequency set by prog pin (default) 01 = 839khz 10 = 723khz 11 = 635khz to keep the switching frequency set by prog pin resistor, leave bit<9:8> as it is or write code 00, which sets the same frequency as the prog pin resistor does. 7 not used, when writing, write 0 6 turbo bit<6> enables or disables turbo mode. when the tu rbo function is enabled, bg ate fet turns on in turbo mode. refer to table 24 on page 36 for bgate on/off truth table. 0 = enable (default) 1 = disable 5 amon/bmon function bit<5> enables or disables the current monitor function amon and bmon. 0 = enable amon/bmon (default) 1 = disable amon/bmon bit<5> is only valid in battery only mode. when adap ter is present, amon/bmon is automatically enabled and bit<5> becomes invalid. 4 amon or bmon bit<4> selects amon or bm on as the output of amon/bmon pin. 0 = amon (default) 1 = bmon 3 psys bit<3> enables or disable system power monitor psys function. 0 = disable (default) 1 = enable 2 vsys bit<2> enables or disables the buck-boost charge r switching vsys output. when disabled, ISL9238 and ISL9238a stops switching an d forces bgate fet on. 0 = enable (default) 1 = disable <1:0> low_vsys_prochot# reference bit<1:0> configures the low_vsys_prochot# assertion threshold. 00 = 6.0v (default) 01 = 6.3v 10 = 6.6v 11 = 6.9v for 1-cell configuration, the low_vsys_pro chot# assertion threshold is fixed 2.4v. ISL9238, ISL9238a 27 fn8877.2 november 9, 2016 submit document feedback table 14. control2 register 0x3dh bit bit name description <15:14> trickle charging current bit<15:14> configures th e charging current in trickle charging mode. 00 = 256ma (default) 01 = 128ma 10 = 64ma 11 = 512ma 13 otg function enable debounce time bit<13> configures the otg function debounce time from when ISL9238 and ISL9238a receives the otg enable command. 0 = 1.3s (default) 1 = 150ms 12 two-level adapter current limit function bit<12> enables or disables the two-level adapter current limit function. 0 = disable (default) 1 = enable 11 adapter insertion to switching debounce bit<11> configures the debounce time from adapter insertion to acok asserted high. 0 = 1.3s (default) 1 = 150ms after vdd por, for the first time adapter plugged in, the asgate turn-on delay is always 150ms, regardless of the bit<11> setting. this bit only sets the asgate turn-on delay after asgate turns off at least one-time when vdd is above it por value and bit<11> default is 0 for 1.3s. <10:9> prochot# debounce bit<10:9> configures the prochot# debounce time before its assertion for acprochot# and dcprochot#. 00: 7s (default) 01: 100s 10: 500s 11: 1ms the low_vsys_prochot# has fixed 10s debounce time. <8:6> prochot# duration bit<8:6> configures the minimum duration of prochot# signal once asserted. 000 = 10ms (default) 001 = 20ms 010 = 15ms 011 = 5ms 100 = 1ms 101 = 500s 110 = 100s 111 = 0s 5 asgate in otg mode bit<5> turns on or off the asgate fet in otg mode. 0 = turn on asgate in otg mode (default) 1 = turn off asgate in otg mode 4 cmin reference bit<4> configures the general purpose comparator reference voltage. 0 = 1.2v (default) 1 = 2v 3 general purpose comparator bit<3> enables or disabled the general purpose comparator. 0 = enable (default) 1 = disable 2 cmout polarity bit<2> configures the general purpose comparator output polarity once asserted. the comparator reference voltage is connected at the inverting input node. 0 = cmout is high when cmin is higher than reference (default) 1 = cmout is low when cmin is higher than reference 1 wocp function bit<1> enables or disables the wo c (way overcurrent) fault protection function. 0 = enable wocp (default) 1 = disable wocp 0 battery ovp function bit<0> enables or disables the battery ov (overvoltage) fault protection function. 0 = disable battery ovp (default) 1 = enable battery ovp ISL9238, ISL9238a 28 fn8877.2 november 9, 2016 submit document feedback table 15. control3 register 0x4ch bit bit name description 15 reread prog pin resistor bit<15> re read prog pin resistor or not. 0 = reread prog pin resistor 1 = do not reread prog pin resistor 14 reload aclim when adapter is plugged in bit<14> reload adaptercurrentlimit1 register set by prog pin resistor. 0 = reload adaptercurrentlimit1 register 1 = do not reload 13 autonomous charging termination time bit<13> configures autonomous charging termination time. 0 = 20ms 1 = 200ms <12:11> charger timeout bit<12:11> config ures smbus charger timeout time. 00 = 175s (default) 01 = 87.5s 10 = 43.75s 11 = 5s 10 bgate off bit<10> enables or disables battery ship mode. 0 = idle 1 = force bgate mosfet off (enable battery ship mode) 9 psys gain bit<9> configures the system power monitor psys output gain. 0 = 1.44a/w (default) 1 = 0.723a/w 8 exit idm timer bit<8> configures ideal diode mode exit time r when battery discharge current is less than 300ma. 0 = 40ms (default) 1 = 80ms 7 autonomous charging mode bit<7> enables autonomous charging mode. 0 = enable autonomous charging mode 1 = battery charging current control through smbus 6 ac and cc feedback gain bit<6> configures ac and cc feedback gain for high current. 0 = idle 1 = x0.5 5 input current limit loop bit<5> di sables input curre nt limit loop. 0 = enable input current limit loop 1 = disable input current limit loop 4 input current limit loop when batgone = 1 bit<4> disables input current limit loop when batgone = 1. 0 = enable aclim when batgone = 1 1 = disable aclim when batgone = 1 3 amon/bmon direction bit<3> configures amon/bmon direction. 0 = adapter current monitor/battery charging current monitor 1 = otg output current monitor/ba ttery discharging current monitor 2 digital reset bit<2> reset all smbus register value to por default value. 0 = idle 1 = reset 1 buck-boost switching period bit<1> configures switching period in buck-boost mode 0 = x1 1 = x2 (half switching frequency) 0 otg start-up delay bit<0> shorts otg start-up time 0 = idle 1 = short otg start-up time from 150ms to 1ms when control2 register bit<13> = 1 for 150ms ISL9238, ISL9238a 29 fn8877.2 november 9, 2016 submit document feedback table 16. control4 register 0x4eh bit bit name description <15:8> not used 7 otgcurrent prochot# bit<6> enables or disa bles trigger prochot# with otgcurrent 0 = disable 1 = enable 6 batgone prochot# bit<6> enables or disa bles trigger prochot# with batgone 0 = disable 1 = enable 5 acok prochot# bit<6> enables or disa bles trigger prochot# with acok 0 = disable 1 = enable 4 comparator prochot# bit<6> enables or disables trigge r prochot# with general purpose comparator rising. 0 = disable 1 = enable <3:2> acok falling or batgone rising debounce bit<3:2> configures debounce time from acok falling or batgone rising to prochot# trip. 00 = 2s 01 = 25s 10 = 125s 11 = 250s 1 prochot# clear bit<1> clear prochot#. 0 = idle 1 = clear prochot# 0 prochot# latch bit<0> manually reset prochot#. 0 = prochot# signal auto-clear 1 = hold prochot# low once tripped ISL9238, ISL9238a 30 fn8877.2 november 9, 2016 submit document feedback otg voltage register the otg voltage register contains smbus readable and writable otg mode output regulation volt age reference. the default is 5.004v. this register accepts an y voltage command but only the valid register bits will be written to the register and the maximum value is clamped at 27.456v. otg current register the otg current register contains smbus readable and writable otg current limit. the default is 512ma. this register accepts any current command but only the valid register bits will be written to the register and the maximum values is clamped at 4096ma for r s1 = 20m . . input voltage register the input voltage register contai ns smbus readable and writable input voltage limit. the default is 4.096v. this register accepts any current command but only the valid register bits will be written to the register and the maximum values is clamped at 18.432v. table 17. otgvoltage register 0x49h bit description <2:0> not used <3> 0 = add 0mv of otg voltage 1 = add 12mv of otg voltage <4> 0 = add 0mv of otg voltage 1 = add 24mv of otg voltage <5> 0 = add 0mv of otg voltage 1 = add 48mv of otg voltage <6> 0 = add 0mv of otg voltage 1 = add 96mv of otg voltage <7> 0 = add 0mv of otg voltage 1 = add 192mv of otg voltage <8> 0 = add 0mv of otg voltage 1 = add 384mv of otg voltage <9> 0 = add 0mv of otg voltage 1 = add 768mv of otg voltage <10> 0 = add 0mv of otg voltage 1 = add 1536mv of otg voltage <11> 0 = add 0mv of otg voltage 1 = add 3072mv of otg voltage <12> 0 = add 0mv of otg voltage 1 = add 6144mv of otg voltage <13> 0 = add 0mv of otg voltage 1 = add 12288mv of otg voltage <14> 0 = add 0mv of otg voltage 1 = add 24576mv of otg voltage <15> not used maximum 27456mv table 18. otgcurrent 0x4ah bit description <6:0> not used <7> 0 = add 0ma of otg current 1 = add 128ma of otg current <8> 0 = add 0ma of otg current 1 = add 256ma of otg current <9> 0 = add 0mv of otg current 1 = add 512ma of otg current <10> 0 = add 0mv of otg current 1 = add 1024ma of otg current <11> 0 = add 0mv of otg current 1 = add 2048ma of otg current <12> 0 = add 0mv of otg current 1 = add 4096ma of otg current <15:13> not used maximum 4096ma table 19. input voltage register 0x4bh bit description <7:0> not used <8> 0 = add 0mv of input voltage 1 = add 341.3mv of input voltage <9> 0 = add 0ma of input voltage 1 = add 682.6mv of input voltage <10> 0 = add 0mv of input voltage 1 = add 1365.3mv of input voltage <11> 0 = add 0mv of input voltage 1 = add 2730.6mv of input voltage <12> 0 = add 0mv of input voltage 1 = add 5461.3mv of input voltage <13> 0 = add 0mv of input voltage 1 = add 10922.6mv of input voltage <15:14> not used maximum 18432mv ISL9238, ISL9238a 31 fn8877.2 november 9, 2016 submit document feedback information register the information register contai ns smbus readable information about manufacturing and operating modes. table 21 identifies the bit locations of the information available. table 20. information1 register 0x3ah bit description <3:0> not used <4> bit<4> indicates if the trickle charging mode is active or not. 0 = trickle charging mode is not active 1 = trickle charging mode is active <9:5> not used <10> bit<10> indicates if the low_vsys_prochot# is tripped or not. 0 = low_vsys prochot# is not tripped 1 = low_vsys prochot# is tripped <11> bit<11> indicates if dcprochot# is tripped or not. 0 = dcprochot# is not tripped 1 = dcprochot# is tripped <12> bit<12> indicates if acprochot#/otgcurrentprochot# is tripped or not. 0 = acprochot#/otgcurrentprochot# is not tripped 1 = acprochot#/otgcurrentprochot# is tripped <14:13> bit<14:13> indicates the active control loop. 00 = maxsystemvoltage control loop is active 01 = charging current loop is active 10 = adapter current limit loop is active 11 = input voltage loop is active <15> bit<15> indicates if the internal reference circuit is active or not. bit<15> = 0 indicates that ISL9238 and ISL9238a are in low power mode. 0 = reference is not active 1 = reference is active table 21. information2 register 0x4dh bit description <4:0> program resister read out # of battery cell switching frequency adapter current limit <7:5> bit<7:5> indicates the ISL9238 and ISL9238a operation mode. 001 = boost mode 010 = buck mode 011 = buck-boost mode 101 = otg boost mode 110 = otg buck mode 111 = otg buck-boost mode <11:8> bit<11:8> indicates the ISL9238 and ISL9238a state machine status 0000 = off 0001 = battery 0010 = adapter 0011 = acok 0100 = vsys 0101 = charge 0110 = enotg 0111 = otg 1000 = enldo5 1001 = not applicable 1010 = trim/enchref 1011 = achrg 1100 = cal 1101 = agon/agontg 1110 = wait/psys 1111 = adppsys <12> bit<10> indicates batgone pin status 0 = battery is present 1 = no battery <13> bit<11> indicates if the general purpose comparator output after debounce time 0 = comparator output is low 1 = comparator output is high <14> bit<12> indicates the acok pin status 0 = no adapter 1 = adapter is present <15> not used ISL9238, ISL9238a 32 fn8877.2 november 9, 2016 submit document feedback application information r3? modulator the ISL9238 and ISL9238a uses intersil patented r3? (robust ripple regulator) modulation scheme. the r3? modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. figure 25 conceptually shows the r3? modulator circuit and figure 26 shows the operation principles in steady state. there is a fixed voltage window between vw and comp. this voltage window is called the vw window in the following discussion. the modulator ch arges the ripple capacitor c r with a current source equal to g m (v in -v o ) during pwm on-time and discharges the ripple capacitor c r with a current source equal to g m v o , during pwm off-time, where g m is a gain factor. the c r voltage v cr therefore emulates the inductor current waveform. the modulator turns off the pwm pulse when v cr reaches vw and turns on the pwm pulse when it reaches comp. since the modulator works with v cr , which is large amplitude and noise free synthesized signal, it achieves lower phase jitter than conventional hysteretic mode modulator. figure 27 shows the operation principles during dynamic response. the comp voltage ri ses during dynamic response, turning on pwm pulses earlier and more frequently temporarily, which allows for higher control loop bandwidth than conventional fixed frequency pwm modulator at the same steady state switching frequency. the r3? modulator can operate in diode emulation (de) mode to increase light-load efficiency. in de mode the low-side mosfet conducts when the current is flowing from source-to-drain and does not allow reverse current, emulating a diode. as shown in figure 28 , when lgate is on, the low-side mosfet carries current, creating negative voltag e on the phase node due to the voltage drop across the on-resistance. the ic monitors the current by monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. figure 25. r3? modulator figure 26. r3? modulator operation principles in steady state figure 27. r3? modulator operation principles in dynamic response figure 28. diode emulation comp r i l gm phase c r v w s q pwm l c o v o v cr + + + - - - comp pwm v cr hysteretic window vw pwm vcr vw comp ugate phase il lgate i l i l v cr i l v cr v cr vw ccm/dcm boundary light dcm deep dcm vw vw ccm ISL9238, ISL9238a 33 fn8877.2 november 9, 2016 submit document feedback if the load current is light enough, as figure 28 on page 32 shows, the inductor current will reach and stay at zero before the next phase node pulse and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a and the regulator is in ccm although the controller is in de mode. figure 29 on page 32 shows the operation principle in diode emulation mode at light load. the load gets incrementally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size, therefore is the same, making the inductor current triang le the same in the three cases. the r3? modulator clamps the ripple capacitor voltage v cr in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v cr , naturally stretching the switching period. the inductor current triangles move further apart from each other, such that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light-load efficiency. ISL9238 and ISL9238a buck-boost charger with usb otg the ISL9238 and ISL9238a buck-boost charger drives an external n-channel mosfet bridge comprised of two transistor pairs as shown in figure 30 . the first pair, q1 and q2, is a buck arrangement with the transistor center tap connected to an inductor ?input? as is the case with a buck converter. the second transistor pair, q3 and q4, is a boost arrangement with the transistor center tap connected to the same inductor?s ?output? as is the case with a boost converter. this arrangement supports bucking from a voltage input higher than the battery and also boosting from a voltage input lower than the battery. in buck mode, q1 and q2 turn on and off alternatively, while q3 remains off and q4 remains on. in boost mode, q3 and q4 turn on and off alternatively, while q1 remains on and q2 remains off. in buck-boost mode, q1 and q3 turn on at the same time, q3 turns off and q4 turns on, q1 turns off and q2 turns on and after q2 and q4 turn off at the same time and q1 and q3 turn on again. in otg buck mode, q3 and q4 turn on and off alternatively, while q2 remains off and q1 remains on. in otg boost mode, q1 and q2 turn on and off alternatively, while q4 remains on and q3 remains off. in otg buck-boost mode, q4 and q2 turn on at the same time, q2 turns off and q1 turns on, q4 turns off and q3 turns on and after q3 and q1 turn off at the same time and q4 and q2 turn on again. in otg mode the output sensing point is the csip pin. the ISL9238 and ISL9238a op timizes the operation mode transition algorithm by considering the input and output voltage ratio and the load condition. when adapter voltage v adp is rising and is higher than 94% of the system bus voltage vsys, ISL9238 and ISL9238a will transit from boost mode to buck-boost mode; if v adp is higher than 120% of vs ys, ISL9238 and ISL9238a will forcedly transit from buck-boost mode to buck mode at any circumstance. at heavier load, th e mode transition point changes accordingly to accommodate the duty cycle change due to the power loss on the charger circuit. when the adapter voltage v adp is falling and is lower than 106% the system bus voltage vsys, is l9238 and ISL9238a will transit from buck mode to buck-boost mode; if v adp is lower than 80% of vsys, ISL9238 and ISL9238a wi ll transit from buck-boost mode to boost mode. table 22. operation mode mode q1 q2 q3 q4 buck control fet sync. fet off on boost on off control fet sync. fet buck-boost control fet sync. fet control fet sync. fet otg buck on off sync. fet control fet otg boost sync. fet control fet off on otg buck-boost sync. fet control fet sync. fet control fet figure 30. buck-boost charger topology csin cson csip csop q1 q3 q2 q4 vsys battery system load l1 r s1 r s2 vadp bgate fet v bat 94% 120% 106% 80% vsys vadp vadp buck-boost buck boost boost buck-boost buck ISL9238, ISL9238a 34 fn8877.2 november 9, 2016 submit document feedback when the otg function is enabled with smbus command and otgen pin and if battery voltage v bat is higher than 5.2v, ISL9238 and ISL9238a operates in the otg mode there is one digital bit to control asgate. otg mode is not available for 1-cell battery systems. the ISL9238 and ISL9238a connects the system voltage rail to either the output of the buck-boos t switcher or the battery. in turbo event, the ISL9238 and ISL9238a will turn on the bgate fet to discharge the battery so the battery works with the adapter together to supply the system power. soft-start the ISL9238 and ISL9238a includes a low power ldo with nominal 5v output, which input is or-ed from vbat and adp pins. the ISL9238 and ISL9238a also includes a high power ldo with nominal 5v output, which input is from dcin pin connected to the adapter and the system bus through an external or-ing diode circuit. both ldo outputs are tied to the vdd pin to provide the bias power and gate drive power for the ISL9238 and ISL9238a. vddp pin is the ISL9238 and ISL9238a gate drive power supply input. use an r-c filter to generate the vddp pin voltage from the vdd pin voltage. when v dd >2.7v, the ISL9238 and ISL9238a digital block is activated and the smbus register is ready to communicate with the master controller. when vadp >3.2v, after 1.3s or 150ms debounce time set by control2 register bit<11> (after vdd por, for the first time adapter plugged in, the asgate turn on delay is always 150ms), asgate starts turning on with 10a sink current. during the 1.3s or 150ms debounce time, ISL9238 and ISL9238a uses intersil?s patented technique to check if th e input bus is short or not; if csip <2v or acin <0.8v, asgate will not turn on. the soft-start scheme will carefully bias up the input capacitors and protect the back-to-back asgate fets agains t potential damage caused by the inrush current. use a voltage divider from the adapter voltage to set the acin pin voltage. the ISL9238 and ISL9238a monitors the acin pin voltage to determine the presence of the adapter. once v dd >3.8v, the acin pin voltage exceeds 0.8v and asgate is fully turned on, the ISL9238 and ISL9238a will allow the external circuit to pull up the acok pin. once acok is asserted, ISL9238 and ISL9238a will start switching. the acok is an open-drain output pin indicating the presence of the adapter and readiness of the adapter to supply power to the system bus. the ISL9238 and isl9 238a actively pulls acok low in the absence of the adapter. before asgate turns on, the ISL9238 and ISL9238a will source 10a of current out of the prog pin and read the pin voltage to determine the prog resistor valu e. the prog resistor programs the configurations of the ISL9238 and ISL9238a. in battery only mode, ISL9238 and ISL9238a enters low power mode if only battery is present. vdd is 5v from the low power ldo to minimize the power consumption. v dd becomes 5v once it exits the low power mode such as when psys is enabled. programming charger option the resistor from the prog pin to gnd programs the configuration of the ISL9238 and ISL9238a for the default number of battery cells in series, the default switching frequency, the default adaptercurrentlimit1 register value and autonomous charging function. adaptercurrentlimit2 register default value is 1.5a. table 23 shows the programming options. the ISL9238 and ISL9238a will us e the default number of cells in series as table 23 shows and set the default maxsystemvoltage register value and default mins ystemvoltage register value accordingly. the switching frequency can be changed through smbus control1 register bit<9:8> after por. refer to smbus control1 register programming table on page 26 for detailed description. table 23. prog pin programming options prog-gnd resistance (k ) cell # default switching frequency autonomous charging default aclimit1 reg(a) min typ 1% max 0 1 733khz no 0.476 8.3 8.45 8.6 733khz no 1.5 14.5 14.7 14.9 1mhz no 1.5 20.7 21.0 21.3 1mhz no 0.476 27.7 28.0 28.3 733khz yes 0.476 35.3 35.7 36.1 733khz yes 1.5 42.7 43.2 43.7 2 733khz yes 1.5 51.7 52.3 52.9 733khz yes 0.476 61.2 61.9 62.6 1mhz no 0.476 70.6 71.5 72.4 1mhz no 1.5 81.5 82.5 83.5 733khz no 1.5 92.0 93.1 94.2 733khz no 0.476 104 105 106 3 733khz no 0.476 116 118 120 733khz no 1.5 131 133 135 1mhz no 1.5 145 147 149 1mhz no 0.476 160 162 164 733khz yes 0.476 176 178 180 733khz yes 1.5 194 196 198 4 733khz yes 1.5 212 215 218 733khz yes 0.476 234 237 240 1mhz no 0.476 258 261 264 1mhz no 1.5 284 287 290 733khz no 1.5 312 316 320 733khz no 0.476 344 348 352 1 733khz no 0.476 ISL9238, ISL9238a 35 fn8877.2 november 9, 2016 submit document feedback before asgate turns on, ISL9238 and ISL9238a will source 10a current out of the prog pin and read the prog pin voltage to determine the resistor value. however, application environmental noise may pollute the prog pi n voltage and cause incorrect reading. if noise is a concern, it is recommended to connect a capacitor from the prog pin to gnd to provide filtering. the resistor and the capacitor rc time constant should be less than 40s so the prog pin voltage can rise to steady state before the ISL9238 and ISL9238a reads it. if ISL9238 and ISL9238a is powere d up from the battery, it will not read prog resistor unless psys is enabled through smbus control1 register bit<3>. in battery only mode, whenever psys is enabled, ISL9238 and ISL9238a will read prog pin resistor and reset the configuration to the default. whenever the adapter is plugged in, ISL9238 and ISL9238a will reset the adaptercurrentlimit1 register to the default by reading the prog pin resistor if it is not read before or by loading the previous reading result. if psys is not enabled, ISL9238 and ISL9238a will reset maxsystemvoltage register and minsystemvoltage register to their default values according to the prog pin cell number setting. if psys is enabled, is l9238 and ISL9238a will keep the values in these two registers. by default, the adapter cu rrent sensing resistor r s1 is 20m and battery current sensing resistor r s2 is 10m . using this r s1 =20m ? and r s2 = 10m option would result in 4ma/lsb correlation in the smbus current commands. if r s1 and r s2 values are different from this r s1 = 20m ? and r s2 = 10m option, the smbus comman d needs to be scaled accordingly to obtain the correct current. smaller current sense resistor values reduce the power loss while larger current sense resistor values give better accuracy. if different current sensing resistors are used, the r s1 :r s2 ratio should be kept as 2:1, then psys output can be scaled accordingly to reflect the total system power correctly. the illustration in this datashee t is based on current sensing resistors r s1 = 20m and r s2 = 10m unless specified otherwise. autonomous charging mode the ISL9238 and ISL9238a supports autonomous charging mode. this mode can be enabled/disabled through programming charging option resistor or smbus control3 register bit<7>. when the autonomous charging mode is enabled, this mode can be al so disabled by writing smbus chargingcurrentlimit or maxsystemvoltage command. the ISL9238 and ISL9238a enters to the autonomous charging mode when the battery voltage is lower than maxsystemvoltage -200mv per cell for 1ms debounce time and bgate mosfet is on. in the autonomous charging mode ISL9238 and ISL9238a starts to charger battery with 2a (with r s2 = 10m ), prochot# pin (autonomous charging mode indication pin) is pulled down to gnd and 175s charging timeout timer is disabled. the ISL9238 and ISL9238a exits from autonomo us charging mode when the battery charging current is less than 200ma (with r s2 = 10m ) for 20ms or 200ms in cv loop . this autonomous charging termination time can be set by control3 register bit<13>. the ISL9238 and ISL9238a re-enters autonomous charging mode when the battery voltage is discharged below maxsystemvoltage - 200mv per cell. when isl 9238 and ISL9238a stays in autonomous charging mode for 12hrs, which means the battery charging current is higher than 200ma and the battery can not be charged to maxsystemvoltage for 12hrs, ISL9238 and ISL9238a stops charging the ba ttery and exits autonomous charging mode. battery ship mode ISL9238 and ISL9238a supports battery ship mode. when control3 register bit <10> is 1, bgate mosfet stays off for battery ship mode. de operation in de mode of operation, th e ISL9238 and ISL9238a employs a phase comparator to monitor the phase node voltage during the low-side switching fet on-time in order to detect the inductor current zero crossing. the phas e comparator needs a minimum on-time of the low-side switching fet for it to recognize inductor current zero crossing. if the low- side switching fet on-time is too short for the phase comparator to successfully recognize the inductor zero crossing, the ISL9238 and ISL9238a may lose diode emulation ability. to prevent such a scenario, the ISL9238 and ISL9238a employs a minimum low-side switching fet on-time. when the intended low-side switching fet on-time is shorter than the minimum valu e, the ISL9238 and ISL9238a stretches the switching period in order to keep the low-side switching fet on-time at the mi nimum value, which causes the ccm switching frequency to drop below the set point. power source selection the ISL9238 and ISL9238a auto matically selects the adapter and/or the battery as the source for system power. the bgate pin drives a p-channel mosfet gate that connects/disconnects the battery from the system and the switcher. the asgate pin drives a pair of back-to-back common source pfets to connect/disconnect the adapter from the system and the battery. use of the asgate pin is optional. when battery voltage v bat is higher than 2.4v and the adapter voltage v adp is less than 3.2v, ISL9238 and ISL9238a operates in battery only mode. during battery only mode, ISL9238 and ISL9238a turn on the bgate fet to connect the battery to the system. in battery only mode, the ISL9238 and ISL9238a consumes very low power, less than 20a during this mode. the battery discharging current monitor bmon can be turned on during this mode to monitor the battery discharging current. if the battery voltage v bat is higher than 5.2v, the system power monitor psys function also can be turned on during this mode to monitor system power. in battery only mode, the usb otg function can be enabled when the battery voltage v bat is higher than 5.2v, see ? usb otg (on the go) ? on page 38 for details. ISL9238, ISL9238a 36 fn8877.2 november 9, 2016 submit document feedback when the adapter voltage v adp is more than 3.2v, ISL9238 and ISL9238a turns on asgate. if v dd is higher than 3.8v, ISL9238 and ISL9238a enters in the forward buck, forward boost or forward buck-boost mode depe nding upon the adapter and system voltage vsys duty cycle ratio. the system bus voltage is regulated at the voltage set on th e maxsystemvoltage register. if charge current register is programmed (non-zero), ISL9238 and ISL9238a charges the battery either in trickle charging mode or fast charging mode, as long as batgone is low. battery learn mode the ISL9238 and ISL9238a supports battery learn mode. the ISL9238 and ISL9238a enters battery learn mode when it receives the smbus control command. this mode of operation is used when it is desired to supply the system power from the battery even when the adapter is plugged in, such as calibration of the battery fuel gauge, hence the name ?battery learn mode?. upon entering battery learn mo de the ISL9238 and ISL9238a will turn on the bgate fet. in battery learn mode, the is l9238 and ISL9238a turns on bgate, keeps asgate on but turns off the buck-boost switcher regardless of whether the adapter is present or not. there are three ways of exiting battery learn mode: 1. receive battery learn mode exit command through smbus. 2. battery voltage is less than minsystemvoltage register setting (according to control1 register bit<12> setting). 3. batgone pin voltage goes from logic low to high. in all these cases, the ISL9238 and ISL9238a resumes switching immediately to supply power to the system bus from the adapter in order to prevent sy stem voltage collapse. turbo mode support turbo mode refers to the scenario when the system draws more power than the adapter?s power rating. if the adapter current reaches the adaptercurrentlimit1 register set value (or adaptercurrentlimit2 register set value, if two-level adapter current limit function is enabled), or the adapter input voltage drops to the input voltag e regulation reference set by control0 register 0x39h bit<2>, the ISL9238 and ISL9238a will limit the input power by regula ting the adapter current at adaptercurrentlimit1/2 register set value, or by regulating the adapter voltage at the input voltage regulation reference point. in turbo mode, the system bus voltage vsys will drop automatically or the charging current will drop automatically to limit the adapter input power. if the vsys pin voltage is 150mv lower than the vbat pin voltage, bgate fet will turn on, such that the battery supplies the rest of the power required by the system. if the ISL9238 and ISL9238a detects 150ma charging current or if the battery discharging current is less than 200ma for longer than 40ms or 80ms, it will turn off bgate to exit turbo mode. turbo mode exit timer can be configured through control3 register 0x4c bit<8>. refer to table 24 for bgate control logic. two-level adapter current limit in a real system, turbo event usually does not last very long. it is often no longer than milliseconds, a time length during which the adapter can supply current higher than its dc rating. the ISL9238 and ISL9238a employs a tw o-level adapter current limit in order to fully take advantage of adapter?s surg e capability and minimize the power drawn from the battery. figure 32 shows the two smbus programmable adapter current limit levels, adaptercurrentlimit1 and adaptercurrentlimit2, as well as the durations t1 and t2. the two-level adapter current limit function is initiated when the adapter current is less than 100ma lower than the adaptercurrentlimit1 register setting and it starts at adaptercurrentlimit2 for t2 duration and then changes to adaptercurrentlimit1 for t1 duration before repeating the pattern. these parameters can set adapter current limit with an envelope that al lows the adapter to temporarily output surge current without requiring the charger to enter turbo mode. such operation maximizes battery life. adaptercurrentlimit1 register value can be higher or lower than adaptercurrentlimit2 value. the two-level adapter current limit function can be enabled and disabled through smbus control2 register bit<12>. when the two-level adapter current limit function is disabled, only adaptercurrentlimit1 value is us ed as the adapter current limit and adaptercurrentlimit2 value is ignored. table 24. bgate on/off truth table turbo (control bit) chargecurrent register bgate on/off 0 = enable 1 = disable 0 = zero 1 = nonzero system load not in turbo mode range system load in turbo mode range 00off on 0 1 on for fast charge; trickle charge is enabled on 10off off 1 1 on for fast charge; trickle charge is enabled on figure 32. two-level adapter current limit adaptercurrentlimit1 i_adapter i_system i_battery t2 t1 t t i i adaptercurrentlimit2 t2 t1 ISL9238, ISL9238a 37 fn8877.2 november 9, 2016 submit document feedback current monitor the ISL9238 and ISL9238a provides an adapter current monitor/otg current monitor or a battery charging current monitor/battery discharging current monitor through the amon/bmon pin. the amon output voltage is 18x (csip-csin) and 18x (csin-csip) voltage and the bmon output voltage is 18x (cson-csop) and 36x (csop-cson) voltage. amon and bmon function can be enabled or disabled through smbus control1 register bit<5>, amon or bmon can be selected through smbus control1 register bit<4> and amon/bmon direction can be configured through smbus control3 register bit<3> as table 13 on page 26 shows. psys monitor the ISL9238 and ISL9238a psys pin provides a measure of the instantaneous power consumption of the entire platform. the psys pin outputs a current source described by equation 1 . k psys is based on current sensing resistor r s1 = 20m and r s2 = 10m . v adp is the adapter voltage in volts, i adp is the adapter current in amperes, v bat is the battery voltage and i bat is the battery discharging current. when the battery is discharging, i bat is a positive value; when the battery is being charged, i bat is a negative value. the battery voltage v bat is detected through cson pin to maximize the power monitor accuracy in nvdc configuration trickle charge mode. the r s1 to r s2 ratio must be 2:1 for a valid power calculation to occur. if the resistance values are higher (or lower) than the suggested values mentioned previously, k psys will be proportionally higher (or lo wer). as an example, if r s1 = 10m and r s2 = 5m , then the output current will be half that above for the same power. if the psys information is not needed then any r s1 :r s2 ratio is acceptable. the psys gain can be configured through smbus control3 register bit<9>. the default psys gain is set to 1.44a/w and 0.723a/w psys gain option is available. the psys information includes the power loss of the charger circuit and the actual power delivered to the system. resistor r psys connected between the psys pin and gnd converts the psys information from current to voltage. psys accuracy limits and a typical accuracy scan are shown in figure 33 . the psys function can be enab led or disabled through smbus control1 register bit<3> as shown in table 13 on page 26 . in battery only mode, the psys function cannot work if the battery voltage is less than 5.2v. trickle charging the ISL9238 and ISL9238a supports trickle charging to an overly discharged battery. it can activa te the trickle charging function when the battery voltage is lower than minsystemvoltage setting. the vbat pin is the battery voltage sense point for trickle charge mode. to enable trickle charging, se t chargecurrent register to a non-zero value. to disable tric kle charging, set chargecurrent register to 0. refer to table 24 on page 36 for trickle charging control logic. the trickle charging current can be programmed to be 512ma, 256ma, 128ma or 64ma through smbus control2 register bit<15:14> in table 14 on page 27 . in trickle charging mode, the ISL9238 and ISL9238a regulates the trickle charging current through the buck-boost switcher. another independent control loop controls the bgate fet such that the system voltage is mainta ined at the voltage set in the minsystemvoltage register. the vs ys pin is the system voltage sensing point in trickle charging mode. once the battery voltage is charged the minsystemvoltage register value, the ISL9238 and ISL9238a enters fast charging mode by limiting the charging current at the chargecurrentlimit register setting. system voltage regulation if the battery is absent, or if a battery is present but bgate is turned off, the ISL9238 and is l9238a will regulate the system bus voltage at the maxsystemvoltage register setting. the vsys pin is used to sense the system bus voltage. charger timeout the ISL9238 and ISL9238a includes a timer to insure the smbus master is active and to prevent overcharging the battery. the ISL9238 and ISL9238a will termin ate charging by turning off bgate fet if the charger has not received a write command to the maxsystemvoltage or chargecurrent register within 175s (smbus control3 register bit<12:11> = 00). charger timeout time can be configured through smbus control3 register bit<12:11>. when the charging is terminated by the timeout, the chargecurrent register will retain its value instea d of resetting to zero. if a timeout occurs, maxsystemvoltage or chargecurrent register must be written to re-enable charging. the ISL9238 and ISL9238a allows users to disable the charger timeout function thro ugh smbus control0 register bit<7> as table 12 on page 25 shows. figure 33. psys accuracy and limits i psys k psys v adp i adp ? v bat i bat ? + ?? ? = (eq. 1) ISL9238, ISL9238a 38 fn8877.2 november 9, 2016 submit document feedback usb otg (on the go) when the otg function is enabled with smbus command and otgen pin and if battery voltage v bat is higher than 5.2v, ISL9238 and ISL9238a operates in the reverse buck, reverse boost, or reverse buck-boost mode. once ISL9238 and ISL9238a rece ives the command to enable the otg function, it will start switching after the 1.3s or 150ms debounce time set by control2 register bit<13>. once the otg output voltage reaches to the otg output voltage set by register 0x49 bit<14:3>, otg power-good otgpg will assert to high. moreover, control2 register bit<5> can be used to turn asgate fet off to cut off the otg output. before otg mode starts switching, the csip pin voltage needs to drop below the otg output over voltage protection threshold (otgvdav + 100mv) first. the default otg output voltage is programmable up to 20v. the otg voltage register 0x49h can be used to configure the otg output voltage. the default otg output current is limited at 512ma through r s1 . the otgcurrent register 0x4ah can be used to adjust the otg output current limit. the ISL9238 and ISL9238a includes the otg output undervoltage and overvoltage pr otection functions. the uvp threshold is otg output voltage -1.2v and the ovp threshold is otg output voltage +1.2v. once uv is detected, ISL9238 and ISL9238a will stop switching and turn off asgate and deassert otgpg after 32ms and after 1.3s or 150ms debounce time set by control2 register bit<13>, it will resume switching. once ov is detected, ISL9238 and ISL9238a will stop switching and deassert otgpg. it will resu me switching after 100s once otg voltage drops below the otg ov threshold. batgone needs to be low to enable otg mode. otg mode is not available for 1-cell battery systems. stand-alone comparator the ISL9238 and ISL9238a in cludes a general purpose stand-alone comparator. otgen/ cmin pin is the comparator input. the internal comparator reference is connected to the inverting input of the comparator and can be configured as 1.2v or 2v through smbus control2 re gister bit<4>. the comparator output is the otgpg/cmout pin and the output polarity when the comparator is tripped can be configured through smbus register bit. when control2 register bit<2> = 0 for normal comparator output polarity, if cmin>reference, cmou t = high; if cmin < reference, cmout = low. when control2 register bit<2> = 1 for inversed comparator output polarity, if cmin>reference, cmout = low; if cmin < reference, cmout = high. in battery only mode, the stand-alone comparator is disabled unless psys is enabled through smbus control1 register bit<3> to enable the internal reference, which is indicated through information1 register bit<15>. table 25 shows the otg mode and the stand-alone comparator truth table. table 25. otg and comparator truth table description control1 register 0x3c control2 register 0x3d pin-2o pin-26 bit<11> otg function enable/disable bit<3> comparator enable/disable otgen/cmin otgpg/cmout 0 0 comparator input pin cmin comparator output pin cmout otg function is disabled. comparator is enabled. 0 1 x x both otg function and comparator are disabled. 1 0 comparator input pin cmin comparator output pin cmout both otg function and comparator are enabled. otg function is enabled when v bat > 5.2v and control1 register bit<11> = 1 without otg power-go od pin indication. while the information1 register 0x3a bit<6:5> = 11 indicates it is in otg mode. 11otg enable input pin otgen otg power-good indication pin otgpg comparator is disabled. otg function is enabled when v bat > 5.2v and enotg pin = high and control1 register bit<11> = 1 ISL9238, ISL9238a 39 fn8877.2 november 9, 2016 submit document feedback adapter overvoltage protection if the adp pin voltage exceeds 23.4v for more than 10s, the ISL9238 and ISL9238a will consider an adapter overvoltage condition has occurred. it will turn off the asgate mosfets to isolate the adapter from the system, deassert the acok signal by pulling it low and stop switching. bgate will turn on for the battery to support the system load. once adp voltage drops below 23.04v from more than 100s, it will start to turn on asgate and start switching. battery overvoltage protection if the vbat pin voltage is higher than battery overvoltage threshold (vbov) + maxsystemvoltage for 1ms, it will declare the battery overvoltage and stop switching. battery overvoltage threshold are 4% of maxsystemvoltage for 1-cell battery setting and 2% of maxsystemvoltage in 2-, 3- and 4-cells setting. it will resume switching with 1ms debounce time when vbat pin voltage drops 0.5xvbov + maxsystemvoltage. the ISL9238 and ISL9238a allows users to disable the battery overvoltage protection function through smbus co ntrol2 register bit<0>. system overvoltage protection the ISL9238 and ISL9238a provid es system rail overvoltage protection. if the system voltage vsys is 800mv higher than maxsystemvoltage register set valu e, it will declare the system overvoltage and stop switching. it will resume switching without the 1.3s or 150ms debounce once vsys drops 300mv below the system overvoltage threshold. way overcurrent protection (wocp) in the case that the system bus is shorted, either a mosfet short or an inductor short, the input current could be high. the ISL9238 and ISL9238a includes input overcurrent protection to turn off the asgate and stop switching. the ISL9238 and ISL9238a provides adapter current and battery discharging current wocp (way overcurrent protection) function against the mosfet short, system bus short and inductor short scenarios. the ISL9238 and ISL9238a monitors the csip-csin voltage and cson-csop voltage, compares them with the wocp threshold 12a for adapter current and 20a for battery discharge current. when the woc comparator is tripped, ISL9238 and ISL9238a counts one time within each 10s . whenever ISL9238 and ISL9238a counts woc to 7 times in 50ms , it turns off asgate, deasserts acok and stops switching immediately. after the 1.3s or 150ms debounce time set by co ntrol2 register bit<11>, it goes through the start-up sequence to retry. the wocp function can be disabled through control2 register bit<1>. over-temperature protection the ISL9238 and ISL9238a will stop switching for self protection when the junction temperature exceeds +140c. once the temperature falls below +120c and after 100s delay, the ISL9238 and ISL9238a will start to switching. switching power mosfet gate capacitance the ISL9238 and ISL9238a include an internal 5v ldo output at vdd pin, which can be used to provide the switching mosfet gate driver power through vddp pin with an r-c filter. the 5v ldo output overcurrent protection threshold is 100ma nominal. when selecting the switching power mosfet, the mosfet gate capacitance should be considered carefully to avoid overloading the 5v ldo, especially in buck -boost mode when four mosfets are switching at the same time. for one mosfet, the gate drive current can be estimated by equation 2 : where: ?q g is the total gate charge, which can be found in the mosfet datasheet ?f sw is switching frequency adapter input filter the adapter cable parasitic inductance and capacitance could cause some voltage ringing or an overshoot spike at the adapter connector node when the adapter is hot plugged in. this voltage spike could damage the asgate mosfet or the ISL9238 and ISL9238a pins connecting to th e adapter connector node. one low cost solution is to add an rc snubber circuit at the adapter connector node to clamp the voltage spike as shown in figure 34 . a practical value of the rc snubber is 2.2 to 2.2f while the appropriate values and power rating should be carefully characterized based on the actual design. meanwhile it is not recommended to add a pure capacitor at the adapter connector node, which can cause an even bigger voltage spike due to the adapter cable or the adapter current path parasitic inductance. figure 34. adapter input rc snubber circuit i driver q g f ? sw = (eq. 2) ISL9238, ISL9238a acin asgate adapter connector r i c i 2.2 2.2f rc snubber ISL9238, ISL9238a 40 fn8877.2 november 9, 2016 submit document feedback general application information this design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase power converter. it is assumed that the reader is familia r with many of the basic skills and techniques referenced in the fo llowing section. in addition to this guide, intersil provides complete reference designs that include schematics, bill of materials and example board layouts. select the lc output filter the duty cycle of an ideal buck converter in ccm is a function of the input and the output voltage. this relationship is written by equation 3 : the output inductor peak-to-peak ripple current is written by equation 4 : a typical step-down dc/dc converter will have an i p-p of 20% to 40% of the maximum dc output load current for a practical design. the value of i p-p is selected based upon several criteria such as mosfet switching loss, inductor core loss and the resistive loss of the inductor winding. the dc copper loss of the inductor can be estimated by equation 5 : where i load is the converter output dc current. the copper loss can be significant so attention has to be given to the dcr selection. another factor to consider when choosing the inductor is its saturation characte ristics at elevated temperatures. a saturated inductor could cause destruction of circuit components. a dc/dc buck regulator must have output capacitance c o into which ripple current i p-p can flow. current i p-p develops a corresponding ripple voltage v p-p across c o, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in and out of the capacitor. these two voltages are written by equations 6 and 7 : if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v p-p is achieved. the inductance of the capacitor can caus e a brief voltage dip if the load transient has an extremely high slew rate. low inductance capacitors should be considered in this scenario. a capacitor dissipates heat as a function of rms current and frequency. be sure that i p-p is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rated value of a capacitor can fade as much as 50% as the dc voltage across it increases. select the input capacitor the important parameters for the input capacitance are the voltage rating and the rms current rating. for reliable operation, select capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the rms current required by the switching circuit. their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. figure 35 is a graph of the input capacitor rms ripple current, normalized relative to output load current, as a function of duty cycle and is adjusted for converte r efficiency. the normalized rms ripple current calculation is written as equation 8 : where: ?i max is the maximum continuous i load of the converter ? k is a multiplier (0 to 1) corresponding to the inductor peak-to peak ripple amplitude expressed as a ratio of i max (0 to 1) ? d is the duty cycle that is adjusted to take into account the efficiency of the converter, which is written as equation 9 : in addition to the capacitance, some low esl ceramic capacitance is recommended to decouple between the drain of the high-side mosfet and the source of the low-side mosfet. d v out v in --------------- = (eq. 3) (eq. 4) i p-p v out 1d C ?? ? f sw l ? ------------------------------------- - = p copper i load 2 dcr ? = ? v esr i p-p e ? sr = (eq. 6) v c i p-p 8c o f ? sw ? ----------------------------- = (eq. 7) (eq. 8) i c in rms normalized , ?? i max d1d C ?? ? dk 2 ? 12 -------------- + ? i max --------------------------------------------------------------- -------- = d v out v in eff ? -------------------------- = (eq. 9) figure 35. normalized rms input current at eff = 1 normalized input rms ripple current duty cycle 00.1 0.2 0.3 0.4 0.6 0.7 0.8 0.9 1.0 0.5 0 0.12 0.24 0.36 0.48 0.60 k = 0.75 k = 0.5 k = 0.25 k = 0 v s = 2.5v k = 1 ISL9238, ISL9238a 41 fn8877.2 november 9, 2016 submit document feedback select the switching power mosfet typically, a mosfet cannot tolerate even brief excursions beyond their maximum drain-to-source vo ltage rating. the mosfets used in the power stage of the conver ter should have a maximum vds rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltag e spike that occurs when the mosfet switches off. there are several power mosfets readily available that are optimized for dc/dc converter applications. the preferred high-side mosfet emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. unlike the low-side mosfet, which has the drain-to-source voltage clamped by its body diode during turn off, the high-side mosfet turns off with a vds of approximately vin - vout, plus the spike across it. the preferred lo w-side mosfet emphasizes low r ds(on) when fully saturated to minimize conduction loss. it should be noted that this is an optimal configuration of mosfet selection for low duty cycle applications (d < 50%). for higher output, low input voltage solutions, a more balanced mosfet selection for high- and low-side devices may be warranted. for the low-side (ls) mosfet, the power loss can be assumed to be conductive only and is written as equation 10 : for the high-side (hs) mosfet, th e conduction loss is written by equation 11 : for the high-side mosfet, the switching loss is written as equation 12 : where: ?i valley is the difference of the dc component of the inductor current minus 1/2 of the inductor ripple current ?i peak is the sum of the dc component of the inductor current plus 1/2 of the inductor ripple current ?t sw(on) is the time required to dr ive the device into saturation ?t sw(off) is the time required to drive the device into cut-off select the bootstrap capacitor the selection of the bootstra p capacitor is written by equation 13 : where: ?q g is the total gate charge required to turn on the high-side mosfet ? ? v boot , is the maximum allowed voltage decay across the boot capacitor each time the hi gh-side mosfet is switched on. as an example, suppose the high-side mosfet has a total gate charge q g , of 25nc at v gs = 5v and a ? v boot of 200mv. the calculated bootstrap capacitance is 0.125f; for a comfortable margin, select a capacitor that is double the calculated capacitance. in this example, 0.22f will suffice. use an x7r or x5r ceramic capacitor. (eq. 10) p con_ls i load 2 r ? ds on ?? _ls 1d C ?? ? ? p con_hs i load 2 r ? ds on ?? _hs d ? = p sw_hs v in i valley t swon f ? sw ? ? 2 --------------------------------------------------------------- ----------- v in i peak t swoff f ? sw ? ? 2 --------------------------------------------------------------- ------- - + = c boot q g ? v boot ----------------------- - = (eq. 13) ISL9238, ISL9238a 42 fn8877.2 november 9, 2016 submit document feedback layout pin number pin name layout guidelines bottom pad 33 gnd connect this ground pad to the ground plane through low impedance path. recommend use of at least 5 vias to connect to ground planes in pcb to ensure there is sufficient thermal dissipation directly under the ic. 1 cson run two dedicated trace with decent width in parallel (c lose to each other to minimize the loop area) from the two terminals of the battery current sensing resistor to the ic . place the differential mode and common-mode rc filter components in general proximity of the controller. route the current sensing traces through vias to connect the ce nter of the pads; or route the traces into the pads from the inside of the current sensing resistor. the following drawings show the two preferred ways of routing current sensing traces . 2csop 3 vsys signal pin. provides feedback for the system bus voltage. place the optional rc filter in general proximity of the controller. run a dedicated trace from system bus to the pi n and do not route near the sw itching traces. do not share the same trace with the signal ro uting to the dcin pin or diodes. 4 boot2 switching pin. place the bootstrap capacitor in general proximity of the controller. use decent wide trace. avoid any sensitive analog signal trace from crossing over or getting close. 5 ugate2 run these two traces in parallel fashion with decent width. avoid any sensitive analog signal trace from crossing over or getting close. recommend routing phase2 trace to high-side mosfet so urce pin instead of general copper. the ic should be placed close to the switching mosfets ga te terminals and keep the gate drive signal traces short for a clean mosfet drive. the ic can be placed on the opposite side of the switching mosfets. place the output capacitors as close as possible to the switching high-side mosfet drain and the low-side mosfet source; and use shortest pcb trace co nnection. place these capacitors on the same pcb layer with the mosfets instead of on different layers and using vias to make the connection. place the inductor terminal to the switching high-side mosf et drain and low-side mosfet source terminal as close as possible. minimize this phase node area to lower the el ectrical and magnetic field radiation but make this phase node area big enough to carry the current. place the indu ctor and the switching mosfets on the same layer of the pcb. 6phase2 7 lgate2 switching pin. run lgate2 trace in parallel with ugat e2 and phase2 traces on the same pcb layer. use decent width. avoid any sensitive analog signal tr ace from crossing over or getting close. 8 vddp place the decoupling capacitor in general proximity of the controller. run the trace connecting to vdd pin with decent width. 9 lgate1 switching pin. run lgate1 trace in parallel with ugat e1 and phase1 traces on the same pcb layer. use decent width. avoid any sensitive analog signal tr ace from crossing over or getting close. 10 phase1 run these two traces in parallel fa shion with decent width. avoid any sensitiv e analog signal trace from crossing over or getting close. recommend routing phase1 trace to high-side mosfet so urce pin instead of general copper. the ic should be placed close to the switching mosfets ga te terminals and keep the gate drive signal traces short for a clean mosfet drive. the ic can be placed on the opposite side of the switching mosfets. place the input capacitors as close as possible to the switching high-side mosfet drain and the low-side mosfet source; and use shortest pcb trace co nnection. place these capacitors on the same pcb layer with the mosfets instead of on different layers and using vias to make the connection. place the inductor terminal to the switching high-side mosf et drain and low-side mosfet source terminal as close as possible. minimize this phase node area to lower the el ectrical and magnetic field radiation but make this phase node area big enough to carry the current. place the indu ctor and the switching mosfets on the same layer of the pcb. 11 ugate1 current sensing traces vias current sensing traces ISL9238, ISL9238a 43 fn8877.2 november 9, 2016 submit document feedback 12 boot1 switching pin. place the bootstrap capacitor in general proximity of the controller. use decent wide trace. avoid any sensitive analog signal trace from crossing over or getting close. 13 asgate run this trace with decent width in parallel fashion with the adp pin trace. 14 csin run two dedicated trace with decent width in parallel (c lose to each other to minimize the loop area) from the two terminals of the adapter current sensing resistor to the ic . place the differential mode and common-mode rc filter components in general proximity of the controller. route the current sensing traces through vias to connect the ce nter of the pads; or route the traces into the pads from the inside of the current sensing resistor. the following drawings show the two preferred ways of routing current sensing traces . 15 csip 16 adp run this trace with decent width in parallel fashion with the asgate pin trace. 17 dcin place the or diodes and the rc filter in general proximit y of the controller. run the vadp trace and vsys trace to the or diodes with decent width. 18 vdd place the rc filter connecting with vddp pin in general proximity of the controller. run the trace connecting to vddp pin with decent width. 19 acin place the voltage divider resistors and the optional decoupling capacitor in general proximity of the controller. 20 otgen/cmin no special consideration. 21 sda digital pins. no special consideration. run sda and scl traces in parallel. 22 scl 23 prochot# digital pin, open-drain output. no special consideration. 24 acok digital pin, open-drain output. no special consideration. 25 batgone digital pin. place the 100k resistor series in the batgone signal trac e and the optional decoupling capacitor in general proximity of the controller. 26 otgpg/cmout digital pin, open-drain output. no special consideration. 27 prog signal pin. place the prog programming resistor in general proximity of the controller. 28 comp place the compensation components in general proximity of the controller. avoid any switching signal from crossing over or getting close. 29 amon/bmon no special consideration. place the optional rc filter in general proximity of the controller. 30 psys signal pin, current source output. no special consideration. 31 vbat place the optional rc filter in general proximity of the controller. run a dedicated trace from the battery positive connection point to the ic. 32 bgate use decent width trace from the ic to the bgate mosfet gate. place the capacitor from bgate to ground close to the mosfet. layout (continued) pin number pin name layout guidelines current sensing traces vias current sensing traces ISL9238, ISL9238a 44 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8877.2 november 9, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purpos es only and is believed to be accurate, however, not warranted. please go to the web to make sure that you have the latest revision. date revision change november 9, 2016 fn8877.2 remove the ISL9238ai rtz parts from ordering information table. updated pod l32.4x4d. changes: added 0.035 nominal value to standoff height september 7, 2016 fn8877.1 increased hbm esd from 1.5kv to 2kv. updated applications and 1st paragraph to include more broad applications. august 31, 2016 fn8877.0 initial release ISL9238, ISL9238a 45 fn8877.2 november 9, 2016 submit document feedback package outline drawing l32.4x4d 32 lead thin quad flat no-lead plastic package rev 2, 10/16 pin #1 6 index area typical recommended land pattern top view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05. tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.25mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail x 0.00 min 0.05 max 5 0.2 ref c bottom view index area pin 1 6 (4x) 0.10 4.00 a b 4.00 b 0.10 ma c 28x 0.40 2.80 2.70 0.10 32x 0.20 4 32x 0.30 b (32x 0.50) (28x 0.40) (32x 0.20) (2.80) (3.90 typ) ( 2.70) see detail x 0.08 c seating plane 0.75 base plane c c 0.10 // side view 0.035 nominal for the most recent package outline drawing, see l32.4x4d . |
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